EmbDev.net

Forum: FPGA, VHDL & Verilog independent process list


Author: mansoor sharifi (Company: shahroodut) (mansoor64)
Posted on:

Rate this post
0 useful
not useful
Hi
how can the sinsivty list in process be independent from each other?
for a example in process(clk1,clk2) a piece of process not run when
change clk1.
the Rising_edge(clk1) or clk1'event not useful,because they can be used 
only once.
this is wrong:
--===========
process(clk1,clk2)
begin
if(rising_edge(clk1))then
out1<=a;
.
.
.
end if;
if(rising_edge(clk2))then
out1<=b;
.
.
.
end if;
end process;
--===========
I wrote my own code in Xilinx7 and Xilinx12.
the error message this:
"signal out1 can not be synthesized, bad synchronous description".
Thanks for your attention

Author: Joe (Guest)
Posted on:

Rate this post
0 useful
not useful
heeehhh?

Author: Lothar Miller (lkmiller) (Moderator)
Posted on:

Rate this post
0 useful
not useful
The actual problem is: out1 is a flipflop. That's a fact, because any 
component reacting to an signals edge will result in a flipflop.
And then: there are no "dual clock input" flipflops in the world.

Why do you need two clocks in your design?
A beginners design has exactly 1 clock all over the FPGA.

Author: mansoor sharifi (Company: shahroodut) (mansoor64)
Posted on:

Rate this post
0 useful
not useful
thanks a lot,
I realized what my problem was.

Reply

Entering an e-mail address is optional. If you want to receive reply notifications by e-mail, please log in.

Rules — please read before posting

  • Post long source code as attachment, not in the text
  • Posting advertisements is forbidden.

Formatting options

  • [c]C code[/c]
  • [avrasm]AVR assembler code[/avrasm]
  • [vhdl]VHDL code[/vhdl]
  • [code]code in other languages, ASCII drawings[/code]
  • [math]formula (LaTeX syntax)[/math]




Bild automatisch verkleinern, falls nötig
Note: the original post is older than 6 months. Please don't ask any new questions in this thread, but start a new one.