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Forum: FPGA, VHDL & Verilog coding the vga port


Author: keith dunc (Company: univ) (kth)
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im trying to display a red box on a 640 by 480 screen however nothing is 
displayed on my vga screen im using nexys 3 and these were the port used
clk v10 ns-n6 vs -p7 red1 -u7 green2 - p8 blue2 -r7 here under is my 
code which i made thanks i appriate any help
 library IEEE; 
use IEEE.std_logic_1164.all; 
use IEEE.std_logic_arith.all; 
use IEEE.std_logic_misc.all; 
use IEEE.std_logic_unsigned.all; 

entity vga is
  port(clk :in std_logic;
      hs : out std_logic;
      vs : out std_logic;
      red1 : out std_logic;
      green2 : out std_logic;
     
blue2: out std_logic
     
      );
            end vga;

Architecture vga_arch of vga is
 
  begin 
       
   
   process(CLK) 
           
         
      
      variable v :std_logic:= '0';
      variable h : std_logic := '1' ;
      variable red :std_logic:= '0';
      variable green :std_logic:= '0';
      variable blue :std_logic:= '0';
       variable x : std_logic_vector(9 downto 0) := "0000000000"  ;
       variable y  : std_logic_vector(9 downto 0) := "0000000000"  ;
      
       
     begin

              
if (CLK'EVENT and CLK = '1') then
 
      if(h = '1') then 
        x := x+ "0000000001" ;
        if(x = "1010000001") then
          h:= '0';
          v := '1';
          x := "0000000000";
        end if;
    elsif(v = '1') then
    y := y + "0000000001";
     V:='0';
     h:='1';
      end if;
      if(y = "0111100001") then 
        y := "0000000000";
      end if;
      hs <= h;
      vs<= v;
      red1 <='1';
      blue2 <='0';
      green2 <='0';
      
       end if;
    end process;
    end vga_arch;

Author: Gustl Buheitel (-gb-)
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Author: keith dunc (Company: univ) (kth)
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i arange the code to 60 hz clock cycle but still nothing

Author: Gustl Buheitel (-gb-)
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http://tinyvga.com/vga-timing/640x480@60Hz

You have to implement everything, front-porch, back-porch, sync-pulse 
...
This is my 1024x768 pixel vga. you can us ist freely and fit it to your 
needs (adapt the timings).
In my case gave the horizontal and vertical counters OUT and generated 
in another module the bin IN signal. This draws an white pixel when bin 
is 1.
The needed 75mhz clock can be generated using an dcm.
--1024x768 VGA
--if bin='1' then pixel is white

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;

entity vga is
  port(clk75_in, bin  : in std_logic;
     horizontal_counter : out std_logic_vector (10 downto 0);
     vertical_counter   : out std_logic_vector (9 downto 0);
       red_out   : out std_logic_vector(2 downto 0);
       green_out : out std_logic_vector(2 downto 0);
       blue_out  : out std_logic_vector(1 downto 0);
       hs_out    : out std_logic;
       vs_out    : out std_logic);
end vga;

architecture Behavioral of vga is

signal hc: integer range 0 to 1328;
signal vc: integer range 0 to 806;

begin
horizontal_counter <= std_logic_vector(to_unsigned(hc,11));
vertical_counter <= std_logic_vector(to_unsigned(vc,10));

--Picture starts with sync-pulse
process
begin
  wait until rising_edge(clk75_in);
    if (hc >= 280 ) -- 280 = Sync-pulse + Back-porch
    and (hc < 1304 ) -- 1304 = Sync-pulse + Back-porch + Visible-area
    and (vc >= 35 ) -- 35 = Sync-pulse + Back-porch
    and (vc < 803 ) -- 803 = Sync-pulse + Back-porch + Visible-area
    then
    if bin = '1' then
      red_out <= "111";
      green_out <= "111";
      blue_out <= "11";
    elsif bin = '0' then
      red_out <= "000";
      green_out <= "000";
      blue_out <= "00";
    end if;

    else
      red_out <= "000";
      green_out <= "000";
      blue_out <= "00";
    end if;
    if (hc > 0 )
      and (hc < 136 ) -- 136 = Sync-pulse
    then
      hs_out <= '0';
    else
      hs_out <= '1';
    end if;
    if (vc > 0 )
      and (vc < 6 ) -- 6 = Sync-pulse
    then
      vs_out <= '0';
    else
      vs_out <= '1';
    end if;
    hc <= hc + 1;
    if (hc = 1328) then --1328 = Whole-line
      vc <= vc + 1;
      hc <= 0;
    end if;
    if (vc = 806) then  --806  = Whole-frame    
      vc <= 0;
    end if;
end process;

end Behavioral;

Author: René D. (Company: www.dossmatik.de) (dose)
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In this document is the resolution 640x480 simulated and after fitted on 
spartan3an700 board.

http://www.dossmatik.de/ghdl/ghdl_unisim.pdf              german
http://www.dossmatik.de/ghdl/ghdl_unisim_eng.pdf          english

Author: Kasturi Kishore (kasturikishore)
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anyone pls help me. I want code in vhdl for hexa decimal inputs. what is 
the port command if i like to give hexadecimal input?

Author: Lothar Miller (lkmiller) (Moderator)
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Don't hijack an old thread with a completely different question!
Start a new thread instead!

And then post all of your information belonging to the problem:
Why do you want to read data?
Where does it come from?
Where does is go to?
What should happen with it?

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