http://tinyvga.com/vga-timing/640x480@60Hz
You have to implement everything, front-porch, back-porch, sync-pulse
...
This is my 1024x768 pixel vga. you can us ist freely and fit it to your
needs (adapt the timings).
In my case gave the horizontal and vertical counters OUT and generated
in another module the bin IN signal. This draws an white pixel when bin
is 1.
The needed 75mhz clock can be generated using an dcm.
1 | --1024x768 VGA
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2 | --if bin='1' then pixel is white
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3 |
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4 | library IEEE;
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5 | use IEEE.STD_LOGIC_1164.ALL;
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6 | use IEEE.numeric_std.all;
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7 |
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8 | entity vga is
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9 | port(clk75_in, bin : in std_logic;
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10 | horizontal_counter : out std_logic_vector (10 downto 0);
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11 | vertical_counter : out std_logic_vector (9 downto 0);
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12 | red_out : out std_logic_vector(2 downto 0);
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13 | green_out : out std_logic_vector(2 downto 0);
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14 | blue_out : out std_logic_vector(1 downto 0);
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15 | hs_out : out std_logic;
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16 | vs_out : out std_logic);
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17 | end vga;
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18 |
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19 | architecture Behavioral of vga is
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20 |
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21 | signal hc: integer range 0 to 1328;
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22 | signal vc: integer range 0 to 806;
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23 |
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24 | begin
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25 | horizontal_counter <= std_logic_vector(to_unsigned(hc,11));
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26 | vertical_counter <= std_logic_vector(to_unsigned(vc,10));
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27 |
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28 | --Picture starts with sync-pulse
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29 | process
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30 | begin
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31 | wait until rising_edge(clk75_in);
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32 | if (hc >= 280 ) -- 280 = Sync-pulse + Back-porch
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33 | and (hc < 1304 ) -- 1304 = Sync-pulse + Back-porch + Visible-area
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34 | and (vc >= 35 ) -- 35 = Sync-pulse + Back-porch
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35 | and (vc < 803 ) -- 803 = Sync-pulse + Back-porch + Visible-area
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36 | then
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37 | if bin = '1' then
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38 | red_out <= "111";
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39 | green_out <= "111";
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40 | blue_out <= "11";
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41 | elsif bin = '0' then
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42 | red_out <= "000";
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43 | green_out <= "000";
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44 | blue_out <= "00";
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45 | end if;
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46 |
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47 | else
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48 | red_out <= "000";
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49 | green_out <= "000";
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50 | blue_out <= "00";
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51 | end if;
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52 | if (hc > 0 )
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53 | and (hc < 136 ) -- 136 = Sync-pulse
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54 | then
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55 | hs_out <= '0';
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56 | else
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57 | hs_out <= '1';
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58 | end if;
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59 | if (vc > 0 )
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60 | and (vc < 6 ) -- 6 = Sync-pulse
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61 | then
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62 | vs_out <= '0';
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63 | else
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64 | vs_out <= '1';
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65 | end if;
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66 | hc <= hc + 1;
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67 | if (hc = 1328) then --1328 = Whole-line
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68 | vc <= vc + 1;
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69 | hc <= 0;
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70 | end if;
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71 | if (vc = 806) then --806 = Whole-frame
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72 | vc <= 0;
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73 | end if;
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74 | end process;
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75 |
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76 | end Behavioral;
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