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Forum: FPGA, VHDL & Verilog Spartan 3 Digital Clock Manager


Author: Vlad Krylov (Company: Kyiv National University) (vlad_)
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Hi guys. I have several questions concerning Digital Clock Manager in 
Spartan-3 and I would be appreciate any help.

1) What does mean "Internal feedback"? How I can assign some register or 
wire in my verilog code to one of DCM's output pins? The User Guide tell 
that it is possible to use internal feedback from CLK0 or from CLK2X 
pin, but how?
2) Is it possible to use somehow DCM's output pin CLKFX with internal 
feedback?

I need to multiply the on-board external clock and to use this 
multiplied clock in my design and now I'm trying to do it without any 
external wires on PCB.

Thanks for help!
Vlad.

Author: Holger (Guest)
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I think you must do it via Synthese command options
See in the header the libs and so.
--------------------------------------------------------------
Code sniplet
See at this Picture ist a VHDL code but invoke by the synthese options.

How it works
------------
http://en.wikipedia.org/wiki/Phase-locked_loop
------------------------------------------------
Hint: can you look for a code sample in VHDL because ist
XILINX SPARTAN is more used in VHDL.
Later may you can WRAP it in VERILOG.
Fist:
If you have a working LED blinki in VHDL you can proof and understand 
that
it runs on your SPARTAN TestBoard. I think ??
Good luck.

Author: Holger (Guest)
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Notice *** This Upper Picture is for Lattice only.

######################################################################## 
##
Hint:
But you can Download for free the Lattice Diamond 1.4 to check it out,
how the implement it there. By attributes for Place & Rout.
Because see in "xapp462.pdf" Spartan the dedicaded routing Path.
To Couple the Master clk over _clk via UCF & Synthese. + Place @Routing 
..
Tool-Chaining.
------------------------------------------------------------------------ 
-
Via main module with Clock Gearbox..[][][][]-() to wire_modulo[][][][]
Hint: user1_clock_PLL  <= ~_c_clk /*Master Clock*/
-----------------------------------------------------------------------
######################################################################## 
#

This is the info pdf for Xilinx DCM on
http://www.xilinx.com/support/documentation/applic...

######################################################################## 
##

Verilog DCM Reference Files link is not valid any more.
            But I will find out, because i need Info for my Lattice 
MachX0
            Control Developer Kit, in Verilog.
######################################################
http://www.xilinx.com/bvdocs/appnotes/xapp462_verilog.
Verilog sample for DCM is not found any more ????.

Good Luck.

Author: Holger (Guest)
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Hello new pdf  sample inside the doku.
http://www.xilinx.com/support/documentation/user_g...
114 www.xilinx.com Spartan-6 FPGA Clocking Resources
UG382 (v1.7) July 20, 2012
Chapter 3: Phase-Locked Loops
Differential BUFIO2FB Zero Delay Buffer Example (Verilog)
IBUFDS_DIFF_OUT INST_IBUFDS_DIFF_OUT (
.I (CLKFB_IN_P),
.IB (CLKFB_IN_N),
.OB (CLKFB_IBUFDS_OB));
BUFIO2FB INST_BUFIO2FB (
.I (~ CLKFB_IBUFDS_OB),
.O (CLK_FEEDBACK_TO_PLL));
Differential BUFIO2FB Zero Delay Buffer Example (VHDL)
I_IBUFGDS: IBUFGDS_DIFF_OUT PORT MAP(
I => CLKFB_IN_P, IB =>
CLKFB_IN_N, OB => CLKFB_OB);
CLKFB_OB_180 <= not CLKFB_OB;
I_BUFIO2FB: BUFIO2FB PORT MAP (
I => CLKFB_OB_180,
O => CLKFB_BUFIO2FB);
Good Luck.
Hint:
In Main Module you submit the clock to the modules
so you can cange the clock for a special module to debug in
tick tick single step mode. So it is flexibe to reach the clock thrue a
wire-trigger_Vector
and not use direct the clock defined in the UCF File.
sniplet:
 

// prom_init.hex
// KEY_CODE[1] co.asm Sub_@Routine read_uptime:
// : Uuptime (     ); 
uuptime_wb #( 
  .CLK_IN_HZ(62500000)
  ) ATIME_INST( /*######## alias TIME_INST */
  .clk_ii(clk), // .clk_ii koppel an clk 62,5Mhz Oszi. Mini_Met-Can 
  .rst_i(rst),
  .wb_adr_i(wb_addr[1:0]), // Cut-To Slice as 2Bit_Spur für selectiv. switch CASE_ADDRESS-b11-@hh,b01-@min,b00-@sek 
  .wb_dat_o(data_from_timer),
  .wb_cyc_i(wb_cyc),
  .wb_stb_i(timer_stb),
  .wb_we_i(wb_we),
  .wb_ack_o(timer_ack)
   );

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