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Forum: FPGA, VHDL & Verilog 8bits to 7segments decoder


Author: werner (Guest)
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Hi, im trying to make a 8bits to 3digits 7segments decoder usind a 
double dabble, but there is something wrong with my code and i dont know 
what, can you help me?


library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;

  package my_pkg is 
    function to_bcd (bin : std_logic_vector(7 downto 0)) return std_logic_vector;
  end package my_pkg;

  package body my_pkg is 
    function to_bcd (bin : std_logic_vector(7 downto 0)) return std_logic_vector is
variable i : integer:=0;
variable bcd : std_logic_vector(11 downto 0) := (others => '0');
variable bint : std_logic_vector(7 downto 0) := bin;

begin
for i in 0 to 7 loop  
bcd(11 downto 1) := bcd(10 downto 0); 
bcd(0) := bint(7);
bint(7 downto 1) := bint(6 downto 0);
bint(0) :='0';


if(i < 7 and bcd(3 downto 0) > "0100") then 
bcd(3 downto 0) := bcd(3 downto 0) + "0011";
end if;

if(i < 7 and bcd(7 downto 4) > "0100") then 
bcd(7 downto 4) := bcd(7 downto 4) + "0011";
end if;

if(i < 7 and bcd(11 downto 8) > "0100") then  
bcd(11 downto 8) := bcd(11 downto 8) + "0011";
end if;


end loop;
return bcd;
end to_bcd;
  end package body my_pkg;



entity termometro is
port (
  clk: in std_logic;
  data: in std_logic_vector(7 downto 0);
  Di: out std_logic_vector (6 downto 0);
  Vtc:out std_logic_vector(3 downto 0));
end termometro;

architecture behavior of termometro is
  signal bcd1, bcd2, bcd3: std_logic_vector(3 downto 0);
  type segs is(se0, se1, se2);
  signal seg_atual, prox_seg: segs;
  signal S1, S2, S3: std_logic_vector(6 downto 0);
  begin
    bcd1<=to_bcd(3 downto 0);
    bcd2<=to_bcd(7 downto 4);
    bcd3<=to_bcd(11 downto 7);
  
  process(bcd1, bcd2, bcd3)
  begin

  WITH bcd1 SELECT
  S1 <= "1111110" when "0000",
      "0110000" when "0001",
      "1101101" when "0010",
      "1111001" when "0011",
      "0110011" when "0100",
      "1011011" when "0101",
      "0100000" when "0110",
      "1110000" when "0111",
      "1111111" when "1000",
      "1111011" when "1001",

      "0000000" when others;
  WITH bcd2 SELECT
  S1 <= "1111110" when "0000",
      "0110000" when "0001",
      "1101101" when "0010",
      "1111001" when "0011",
      "0110011" when "0100",
      "1011011" when "0101",
      "0100000" when "0110",
      "1110000" when "0111",
      "1111111" when "1000",
      "1111011" when "1001",

      "0000000" when others;
  WITH bcd3 SELECT
  S1 <= "1111110" when "0000",
      "0110000" when "0001",
      "1101101" when "0010",
      "1111001" when "0011",
      "0110011" when "0100",
      "1011011" when "0101",
      "0100000" when "0110",
      "1110000" when "0111",
      "1111111" when "1000",
      "1111011" when "1001",

      "0000000" when others;
  
  end process;
  
  process(clk) is
  begin
    if(clk = '1' and clk'event) then
      seg_atual<=prox_seg;
    end if;
  end process;
  
  process (S1, S2, S3) is
    begin  
        case seg_atual is
          when se0=>
            Di <= S1;
            Vtc<= "0001";
            prox_seg <= se1;
          when se1 =>
            Di <= S2;
            Vtc<= "0010";
            prox_seg <= se2;
          when se2 =>
            Di <= S3";
            Vtc<= "0100";
            prox_seg <= se3;
        end case;
      end process;
  
end behavior;

Author: Lothar Miller (lkmiller) (Moderator)
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> but there is something wrong with my code and i dont know what
Do you have a test bench for the code?

> but there is something wrong with my code and i dont know what
Really your code?
    function to_bcd (bin : std_logic_vector(7 downto 0)) return  std_logic_vector;
    
    :
    :

    bcd1<=to_bcd(3 downto 0);   -- 4 bits input for a 8 bit function?
    bcd2<=to_bcd(7 downto 4);f
    bcd3<=to_bcd(11 downto 7);
This looks for me like more like:
"I have copied some pieces of code from somewhere, do not understand 
even one line, and its not working like i expected! Whats wrong?"

So, first try to understand what to_bcd does and how you have to use it.
A hint: you only have to call this function once.



You can do this here much more compact, if you convert only one digit 
(the one to be displayed) and multiplex the bcd input instead of the 
segment /output/:
  process(bcd1, bcd2, bcd3)
  begin

  WITH bcd1 SELECT
  S1 <= "1111110" when "0000",
      :
      "0000000" when others;

  WITH bcd2 SELECT
  S1 <= "1111110" when "0000",
      :
      "0000000" when others;

  WITH bcd3 SELECT
  S1 <= "1111110" when "0000",
      :
      "0000000" when others;

  end process;

Author: werner (Guest)
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i've made this code by using one that i've found on the internet, i used 
a double dabble(and i understud it) code with a sweep code for 7segments 
that i've(not from internet) made sometime ago that showed the word 
'DATE' and 'HORA' for example on a 4digit 7segment display, it showed 1 
letter each clock time on a diferent digit, so i use a realy fast clock 
and it looks like that it was appearing simultaneously, i just try to 
join the 2 codes, i didnt found it anywhere

BUTT i doesnt work, no matter what i try, and i tryed alot, and i dont 
know what is wrong with it, thats why im asking on this forum


but thx for the tip, ill try it

Author: TheMason (Guest)
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One thing i have noticed :

you used copy&paste to decode 4 bits to a 7-segment digit, but you 
forgot to change the destination register.

your bcd1 bcd2 and bcd3 all (!) work on only S1. I think bcd1 should be 
decocded in S1, bcd2 in S2 and bcd3 in S3, i seems to make more sense, 
than using only S1. And anyway, later on you use S2 and S3 without 
having made an assignment. perhaps this is the reason why it won't work.

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