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Forum: FPGA, VHDL & Verilog help with an error


Author: Thomas Turner (tombo88)
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I'm trying to write a behavioural description of  an 8-bit binary 
counter. my code is as follows. I keep getting an error that says:

near text "process"; expecting "if";

the error is on the line that says "end process;". I thought I might not 
have ended one of my if statements but as far as I can tell I have an 
"end if;" for each one of my if statements. just wondering what else I 
might have done wrong. thanks in advance.
Tom Turner

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

entity COUNT8 is

 port(
    CLK  : in  std_logic;
    CLR : in    std_logic;
    DIR : in    std_logic;
    ENA : in    std_logic;
    LOAD  : in  std_logic;
    DATA    : in    std_logic_vector(7 downto 0);
    COUNT  : out  std_logic_vector(7 downto 0)
  );

end COUNT8;

architecture behavior of COUNT8 is
begin
    process(CLK)
    begin
    if (CLR = '0') then
      COUNT <= "00000000";
      else if (CLK'EVENT AND CLK = '1') then
        if (LOAD = '0') then
          if ENA = '1' then
          if DIR = '1' then
            COUNT <= COUNT + 1;
          else
            COUNT <= COUNT - 1;
          end if;
        end if;
      else
        COUNT <= DATA;
        end if;
      end if;
    end process;
end behavior;

Author: user (Guest)
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you want to write "elsif" instead of "else if"

Author: Dariush H. (dariush_h)
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U need to add a
end if;
 just before
end process;
But after setting this right the compiler throwing errors
Error (10309): VHDL Interface Declaration error in COUNT8.vhd(29): interface object "COUNT" of mode out cannot be read. Change object mode to buffer or inout.
Error (10327): VHDL error at COUNT8.vhd(29): can't determine definition of operator ""+"" -- found 0 possible definitions

Author: Lothar Miller (lkmiller) (Moderator)
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With proper formatting your code looks like this:
  process(CLK) begin
     if (CLR = '0') then
        COUNT <= "00000000";
     else 
        if (CLK'EVENT AND CLK = '1') then
           if (LOAD = '0') then
              if ENA = '1' then
                 if DIR = '1' then
                    COUNT <= COUNT + 1;
                 else
                    COUNT <= COUNT - 1;
                 end if;
              end if;
           else
              COUNT <= DATA;
           end if;
        end if;
     ???????
  end process;

What you wanted was this:
  process(CLK) begin
     if (CLR = '0') then
        COUNT <= "00000000";
     elsif (CLK'EVENT AND CLK = '1') then -- an "elsif" is somehow different than an "else if"
        if (LOAD = '0') then
           if ENA = '1' then
              if DIR = '1' then
                 COUNT <= COUNT + 1;
              else
                 COUNT <= COUNT - 1;
              end if;
           end if;
        else
           COUNT <= DATA;
        end if;
     end if;
  end process;

> But after setting this right the compiler throwing errors
1. You cannot read an output.
   Use internal signals instead.

2. You cannot add two std_logic vectors with numeric_std.
   Use unsigned or signed vectors instead.
   Cast between std_logic_vector and unsigned/singed.
   See the picture there:
   http://www.lothar-miller.de/s9y/categories/16-Numeric_Std

Author: Thomas Turner (tombo88)
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thanks this was very helpful. I have changed a few things including 
using a buffer for my count vector.

Author: Dariush H. (dariush_h)
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Its good to know that your problem has been solved.
I have a presentation in next 2 days about VHDL in my university and i 
am collecting some sample project to show in my presentation and your 
8-bit counter seems a good idea.

I wonder to know can your post your corrected version of your codes so i 
can use them in my presentation?

tnx

Author: Lothar Miller (lkmiller) (Moderator)
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Thomas Turner wrote:
> thanks this was very helpful.
De nada.
> I have changed a few things including using a buffer for my count vector.
You did not read my post? It is bad idea to be lazy and NOT to use 
internal signals. You will find this out sooner or later. The major 
problem is that a counter signal is not a buffer but a simple internal 
signal. That was the reason why i wrote:
>>  Use internal signals instead.
I did with full intention not write "use a buffer". Get accustomed to 
the flowery and talky style of VHDL.

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