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Forum: FPGA, VHDL & Verilog Why on Simulation the result is not what is expected?


Author: Dariush H. (dariush_h)
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Hey guys
I have a presentation for next couple days on VHDL and i need to show 
some simple example project, I managed to write a <b>4 Bit Adder</b> as 
follow:
Adder4.vhd:
library ieee;
use ieee.std_logic_1164.all;

ENTITY Adder4 IS
  PORT
  (
    Cin  : IN   STD_LOGIC;
    X, Y : IN   STD_LOGIC_VECTOR   (3 DOWNTO 0);
    R   : OUT   STD_LOGIC_VECTOR  (3 DOWNTO 0);
    Cout : OUT STD_LOGIC
  );
END Adder4;

ARCHITECTURE Adder4_Behav OF Adder4 IS
  SIGNAL Carry : STD_LOGIC_VECTOR ( 2 DOWNTO 0);
  
  COMPONENT FullAdder
    PORT
    (
      Cin, A, B  : IN   STD_LOGIC;
      Cout, S    : OUT   STD_LOGIC
    );
  END COMPONENT;
BEGIN
  FA0: FullAdder PORT MAP ( Cin, X(0), Y(0), Carry(0), R(0));
  FA1: FullAdder PORT MAP ( Carry(0), X(1), Y(1), Carry(1), R(1));
  FA3: FullAdder PORT MAP ( Carry(1),X(2),Y(2),Carry(2),R(2));
  FA4: FullAdder PORT MAP ( Carry(2),X(3),Y(3),Cout,R(3));
END;

FullAdder.vhd
library ieee;
use ieee.std_logic_1164.all;

ENTITY FullAdder IS
  PORT
  (
    Cin, A, B  : IN STD_LOGIC;
    Cout, S    : OUT STD_LOGIC
  );
END FullAdder;

ARCHITECTURE FullAdder_Behav OF FullAdder IS
BEGIN
  S <= A XOR B XOR Cin;
  Cout <= (A AND Cin) OR (B AND Cin) OR (A AND B);
END;

but when i run simulation the output result is not synced at all!
I know i am not considering something here, but what is that?
I need HELP ASAP, please :(
What is it that i am doing wrong!?

I have posted the *.vwf and the simulation result as attachments

Thanks in advace

Author: Lothar Miller (lkmiller) (Moderator)
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Do you perform a timing simulation?
If yes: try it with a functional simulation.
It will be much, much faster...

> but when i run simulation the output result is not synced at all!
Why do you expect something to be sync'ed to something else?
In your design theres no clock, so all of it is completely asynchronous.

BTW: Your design is completely in VHDL. So, why don't you simply use a 
VHDL testbench instead of that manual vector wave drawing?

Author: Dariush H. (dariush_h)
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thanks for ur answer.

First off i am totally newB in VHDL programming so my questions may seem 
silly:)

> Do you perform a timing simulation?
I dont know if i am performing a timing simulation or not! how can i 
know that?


> VHDL testbench instead of that manual vector wave drawing?
I have no idea how can i write a testbeanch for this and how i can run 
that! :(
How can i do testbench and how i can get visual resualts?

Author: Shriniwash (Guest)
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>but when i run simulation the output result is not synced at all!

>I have no idea how can i write a testbeanch for this

How do you run simulation without a testbench?

Author: Dariush H. (dariush_h)
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> How do you run simulation without a testbench?

I create a vector wave drawing in QuartusII and setting input pins some 
values! < see attachment >

Author: Lothar Miller (lkmiller) (Moderator)
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Dariush H. wrote:
> I have no idea how can i write a testbeanch for this and how i can run
> that! :(
> How can i do testbench and how i can get visual resualts?
A testbench is just a VHDL entity without ports. In this entity you 
place your desgins top level entity as a component.

So it will look somehow like this:
library ieee;
use ieee.std_logic_1164.all;

ENTITY Adder4_tb IS
END Adder4_tb;

ARCHITECTURE behave OF Adder4_tb IS
  signal  Cin : STD_LOGIC := '0';
  signal  X :   STD_LOGIC_VECTOR   (3 DOWNTO 0) := ("0000");
  signal  Y :   STD_LOGIC_VECTOR   (3 DOWNTO 0) := ("0000");
  signal  R :   STD_LOGIC_VECTOR   (3 DOWNTO 0);
  signal  Cout: STD_LOGIC;

  COMPONENT Adder4 
    PORT
    (  Cin  : IN   STD_LOGIC;
       X, Y : IN   STD_LOGIC_VECTOR   (3 DOWNTO 0);
       R    : OUT   STD_LOGIC_VECTOR  (3 DOWNTO 0);
       Cout : OUT STD_LOGIC
    )
  END COMPONENT;

BEGIN
  adder: Adder4 PORT MAP (Cin=>Cin, X=>X, Y=>Y, R=>R, Cout=>Cout);

  trestbench: process begin
     Cin <= '0';
     X   <= "0001";
     Y   <= "0001";
     wait for 10 ns;
     assert R = "0010" report "Result wrong!" severity failure; 

     Cin <= '0';
     X   <= "0011";
     Y   <= "0001";
     wait for 10 ns;
     assert R = "0100" report "Result wrong!" severity failure; 

     Cin <= '1';
     X   <= "0001";
     Y   <= "0001";
     wait for 10 ns;
     assert R = "0011" report "Result wrong!" severity failure; 
 
     --- and so on...

  end process;

END;

And you already know how to have a look for the waveform, because that 
analysis end of the simulation is the same as with graphical stimuli.

Author: Dariush H. (dariush_h)
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Thank you Lothar Miller you helped me alot!
cheers

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