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Forum: FPGA, VHDL & Verilog Why on Simulation the result is not what is expected?


Why on Simulation the result is not what is expected?
von Dariush H. (dariush_h)

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Hey guys
I have a presentation for next couple days on VHDL and i need to show 
some simple example project, I managed to write a <b>4 Bit Adder</b> as 
follow:
Adder4.vhd:
1
library ieee;

2
use ieee.std_logic_1164.all;

3
4
ENTITY Adder4 IS

5
  PORT

6
  (

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    Cin  : IN   STD_LOGIC;

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    X, Y : IN   STD_LOGIC_VECTOR   (3 DOWNTO 0);

9
    R   : OUT   STD_LOGIC_VECTOR  (3 DOWNTO 0);

10
    Cout : OUT STD_LOGIC

11
  );

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END Adder4;

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ARCHITECTURE Adder4_Behav OF Adder4 IS

15
  SIGNAL Carry : STD_LOGIC_VECTOR ( 2 DOWNTO 0);

16
  

17
  COMPONENT FullAdder

18
    PORT

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    (

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      Cin, A, B  : IN   STD_LOGIC;

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      Cout, S    : OUT   STD_LOGIC

22
    );

23
  END COMPONENT;

24
BEGIN

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  FA0: FullAdder PORT MAP ( Cin, X(0), Y(0), Carry(0), R(0));

26
  FA1: FullAdder PORT MAP ( Carry(0), X(1), Y(1), Carry(1), R(1));

27
  FA3: FullAdder PORT MAP ( Carry(1),X(2),Y(2),Carry(2),R(2));

28
  FA4: FullAdder PORT MAP ( Carry(2),X(3),Y(3),Cout,R(3));

29
END;


FullAdder.vhd
1
library ieee;

2
use ieee.std_logic_1164.all;

3
4
ENTITY FullAdder IS

5
  PORT

6
  (

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    Cin, A, B  : IN STD_LOGIC;

8
    Cout, S    : OUT STD_LOGIC

9
  );

10
END FullAdder;

11
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ARCHITECTURE FullAdder_Behav OF FullAdder IS

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BEGIN

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  S <= A XOR B XOR Cin;

15
  Cout <= (A AND Cin) OR (B AND Cin) OR (A AND B);

16
END;


but when i run simulation the output result is not synced at all!
I know i am not considering something here, but what is that?
I need HELP ASAP, please :(
What is it that i am doing wrong!?

I have posted the *.vwf and the simulation result as attachments

Thanks in advace

  


  




  

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    Re: Why on Simulation the result is not what is expected?
  


  

    

      von
      
        Lothar M.
            (Company: Titel)
        (lkmiller)
        (Moderator)
      
      


      
    


    

      
    

    

    

  
  


  

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Do you perform a timing simulation?
If yes: try it with a functional simulation.
It will be much, much faster...

> but when i run simulation the output result is not synced at all!
Why do you expect something to be sync'ed to something else?
In your design theres no clock, so all of it is completely asynchronous.

BTW: Your design is completely in VHDL. So, why don't you simply use a 
VHDL testbench instead of that manual vector wave drawing?

  


  




  

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    Re: Why on Simulation the result is not what is expected?
  


  

    

      von
      
        Dariush H.
        (dariush_h)
        
      
      


      
    


    

      
    

    

    

  
  


  

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thanks for ur answer.

First off i am totally newB in VHDL programming so my questions may seem 
silly:)

> Do you perform a timing simulation?
I dont know if i am performing a timing simulation or not! how can i 
know that?


> VHDL testbench instead of that manual vector wave drawing?
I have no idea how can i write a testbeanch for this and how i can run 
that! :(
How can i do testbench and how i can get visual resualts?

  


  




  

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    Re: Why on Simulation the result is not what is expected?
  


  

    

      von
      
        Shriniwash (Guest)
      
      


      
    


    

      
    

    

    

  
  


  

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>but when i run simulation the output result is not synced at all!

>I have no idea how can i write a testbeanch for this

How do you run simulation without a testbench?

  


  




  

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    Re: Why on Simulation the result is not what is expected?
  


  

    

      von
      
        Dariush H.
        (dariush_h)
        
      
      


      
    


    

      
    

    

    

      

      

      Attached files:



        
    

  
  


  

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> How do you run simulation without a testbench?

I create a vector wave drawing in QuartusII and setting input pins some 
values! < see attachment >

  


  




  

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    Re: Why on Simulation the result is not what is expected?
  


  

    

      von
      
        Lothar M.
            (Company: Titel)
        (lkmiller)
        (Moderator)
      
      


      
    


    

      
    

    

    

  
  


  

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Dariush H. wrote:
> I have no idea how can i write a testbeanch for this and how i can run
> that! :(
> How can i do testbench and how i can get visual resualts?
A testbench is just a VHDL entity without ports. In this entity you 
place your desgins top level entity as a component.

So it will look somehow like this:
1
library ieee;

2
use ieee.std_logic_1164.all;

3
4
ENTITY Adder4_tb IS

5
END Adder4_tb;

6
7
ARCHITECTURE behave OF Adder4_tb IS

8
  signal  Cin : STD_LOGIC := '0';

9
  signal  X :   STD_LOGIC_VECTOR   (3 DOWNTO 0) := ("0000");

10
  signal  Y :   STD_LOGIC_VECTOR   (3 DOWNTO 0) := ("0000");

11
  signal  R :   STD_LOGIC_VECTOR   (3 DOWNTO 0);

12
  signal  Cout: STD_LOGIC;

13
14
  COMPONENT Adder4 

15
    PORT

16
    (  Cin  : IN   STD_LOGIC;

17
       X, Y : IN   STD_LOGIC_VECTOR   (3 DOWNTO 0);

18
       R    : OUT   STD_LOGIC_VECTOR  (3 DOWNTO 0);

19
       Cout : OUT STD_LOGIC

20
    )

21
  END COMPONENT;

22
23
BEGIN

24
  adder: Adder4 PORT MAP (Cin=>Cin, X=>X, Y=>Y, R=>R, Cout=>Cout);

25
26
  trestbench: process begin

27
     Cin <= '0';

28
     X   <= "0001";

29
     Y   <= "0001";

30
     wait for 10 ns;

31
     assert R = "0010" report "Result wrong!" severity failure; 

32
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     Cin <= '0';

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     X   <= "0011";

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     Y   <= "0001";

36
     wait for 10 ns;

37
     assert R = "0100" report "Result wrong!" severity failure; 

38
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     Cin <= '1';

40
     X   <= "0001";

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     Y   <= "0001";

42
     wait for 10 ns;

43
     assert R = "0011" report "Result wrong!" severity failure; 

44
 

45
     --- and so on...

46
47
  end process;

48
49
END;


And you already know how to have a look for the waveform, because that 
analysis end of the simulation is the same as with graphical stimuli.

  


  




  

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    Re: Why on Simulation the result is not what is expected?
  


  

    

      von
      
        Dariush H.
        (dariush_h)
        
      
      


      
    


    

      
    

    

    

  
  


  

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Thank you Lothar Miller you helped me alot!
cheers

  


  




  

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