Forum: FPGA, VHDL & Verilog Error in simple code

Author: tino tino (tino09)
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Hello everyone, I am a newbie in VHDL, Im programming a code for 
simulating a T flip flop but all I get are errors.. Right now my code is 
not supossed to do nothing but giving the value '1' to q_temp but Im 
getting this error in line 47 and I dont know why, can anyone help me 

Line 47. Variable 'q_temp' q_temp is at left hand side of signal 
assignment statement.
entity TFF2 is
    Port ( T : in  STD_LOGIC;
           CLK : in  STD_LOGIC;
           Q : out  STD_LOGIC;
           notQ : out  STD_LOGIC);
end TFF2;

architecture Behavioral of TFF2 is


  Tff: process (CLK, T) is
    variable q_temp: std_logic :='0';
       if (clk'event and CLK = '1' and T = '1') then 
      q_temp <= '1';  --LINE 47
     end if;
  end process;
  --q_past <= '1';
 -- Q <= q_temp;
  --Q <= '1';
end Behavioral;

Author: Lothar Miller (lkmiller) (Moderator)
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Try this in line 47:
   q_temp := '1';

And read about the differences between variables and signals.

Author: tino tino (tino09)
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Thank you, thank fixed it. I still have a lot to learn :)


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