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Forum: FPGA, VHDL & Verilog Dual operation with single clock


Author: Sivaprasad KUNDURU (Company: Printed Electronic Ltd) (sivaprasadreddy)
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hi,
Could any one please tell me how to perform dual operation for a single 
clock pluse(rising edge,falling edge/on,off) in VHDL.
thanks in advance.

Author: Lothar Miller (lkmiller) (Moderator)
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What do you need this for? DDR Ram or something likewise?

Author: Sivaprasad KUNDURU (Company: Printed Electronic Ltd) (sivaprasadreddy)
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Yes it is for DDR RAM based application.

Author: Lothar Miller (lkmiller) (Moderator)
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Then the only place you need both edges is the IO cell.
And in the documentation for the IO pins you can find the documentation, 
how to implement a DDR interface. Indeed there is no real "both edge 
flipflop", but two seperate "rising-edge-flipflops", and one of them is 
supplied with the inverted clock. And this DDR cell is usually not 
described in VHDL, but it is a component (black box) provided from the 
manufaturer of the FPGA to be instantiated with a VHDL template...

Author: Sivaprasad KUNDURU (Company: Printed Electronic Ltd) (sivaprasadreddy)
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Thanks for your reply.

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