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Forum: FPGA, VHDL & Verilog VHDL Processes & Sensitivity Lists


Author: Brian Sutin (Company: UT Aerospace Systems) (utas)
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I am modifying some existing VHDL and find the code curious.  A snippet 
is attached with two processes.  In this snippet, A and B are completely 
independent from C and D.  First, is there any reason why the two 
processes could not be combined into one process?  Second, does the test 
for sysclk'event do anything?  I would think that having sysclk on the 
process sensitivity list would have already enforced the process to run 
on an event.  Perhaps the 'if' statement only has an effect on the first 
time the process runs?
process (sysclk) is
begin
    if (sysclk'event and sysclk='1') then
        A <= B;
    end if;
end process;

process (sysclk) is
begin
    if (sysclk'event and sysclk='1') then
        C <= D;
    end if;
end process;

Author: Rainer (Guest)
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You can combine the two processes, it will also work. But if you use a 
seperate process for every signal, it is  clearly arranged.
"if (sysclk'event and sysclk='1') then" means, that this is a clocked 
process. Only on a rising edge of sysclk there will happen something. 
Instead you can also write "if rising_edge(sysclk).

Have a nice day
Rainer

Author: Lothar Miller (lkmiller) (Moderator)
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Brian Sutin wrote:
> I am modifying some existing VHDL and find the code curious.  A snippet
> is attached with two processes.  In this snippet, A and B are completely
> independent from C and D.  First, is there any reason why the two
> processes could not be combined into one process?
It may be in two processes, because the two things are 
independent...

> Second, does the test for sysclk'event do anything?
It tells the synthesizer to generate a flipflop.

> I would think that having sysclk on the process sensitivity list would
> have already enforced the process to run on an event.
The sensitivity list is only for the simulation. It tells the 
simulator when it has to recalculate the process.


So, when you write this
process (sysclk) is
begin
    if (sysclk'event and sysclk='1') then
        A <= B;
    end if;
process;
and this
process (someothersignal) is
begin
    if (sysclk'event and sysclk='1') then
        A <= B;
    end if;
process;
you will get exactly the same hardware, but in the second case the 
simulation will be total nuts...


And this here
process (sysclk) is
begin
    if (sysclk'event and sysclk='1') then
        A <= B;
    end if;
process;
will look exactly the same like this
process (sysclk) is
begin
    if (sysclk='1') then
        A <= B;
    end if;
process;
in simulation, but it will lead to a totally different hardware!
And why? It is because in the second case the sensitivity list is 
missing the signal B, because when sysclk ist '1' then every change on 
B must be transferred to A immediately.

To keep it short: the sensitivity list is only of interest, if you want 
a correctly working simulation. The synthesizer does not use the 
sensitivity list at all!
In the best case synthesis informs you that there may be a misalignment 
between simulation and reality due to an incomplete sensitivity list.

Author: Brian Sutin (Company: UT Aerospace Systems) (utas)
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Thank you for the replies.  Actually I am not simulating this at all; I 
don't even have a simulator.  The code is running on a Xilinx FPGA. 
What would happen if I left out the sensitivity list on hardware?  I 
assume that this would be considered bad programming practice.

Author: Lattice User (Guest)
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Sooner or later you WILL need to simulate do find some nasty bug. And 
when your sensitivy lists are not correct you have a BIG problem.

Author: Lothar Miller (lkmiller) (Moderator)
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When you have Xilinx ISE, then you have the ISIM simulator.

Author: Brian Sutin (Company: UT Aerospace Systems) (utas)
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The project as a whole has 14 Xilinx cores, including Microblaze with 
10,000+ lines of C++ code.  It continuously communicates over Ethernet 
with external computers, and the custom VHDL in question controls such 
things as several high-speed DAC's and ADC's.  Some form of emulation 
would have to be written for all of these interfaces in order to create 
a worthwhile simulation of the changes I am making to the VHDL.  I admit 
that I am not man enough to do all that.  Tweaking the VHDL and running 
on hardware has been good to me so far.

I just wish I felt a little less like "Rogue Moon" when I enter VHDL 
Land.

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