Forum: FPGA, VHDL & Verilog System generator/ VHDL code generator/ partial reconfiguration

Author: deepak singh (dksagra)
Posted on:

Rate this post
0 useful
not useful
I need one help. Please sir if you able to help me i will be very 
grateful for your kind help.

There is one tool in Xilinx, System Generator.
I have prepare one architecture using blocks from Simulink in it. i am 
getting good results
then i have generate the VHDL code through HDL CODE GENERATION.

now i have a VHDL code of the same architecture.

my question is: Now i have to apply Partial Reconfiguration on this VHDL 
code. So Can we apply?
if yes then how can be?

I am looking forward to your reply.


Entering an e-mail address is optional. If you want to receive reply notifications by e-mail, please log in.

Rules — please read before posting

  • Post long source code as attachment, not in the text
  • Posting advertisements is forbidden.

Formatting options

  • [c]C code[/c]
  • [avrasm]AVR assembler code[/avrasm]
  • [vhdl]VHDL code[/vhdl]
  • [code]code in other languages, ASCII drawings[/code]
  • [math]formula (LaTeX syntax)[/math]

Bild automatisch verkleinern, falls nötig
Note: the original post is older than 6 months. Please don't ask any new questions in this thread, but start a new one.