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Forum: FPGA, VHDL & Verilog END OF DATA on FRAME


Author: sagar gaddam (Company: iqi labs) (sagar0205)
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hi
I'm trying to write code for SDI-12 protocol
the byte frame format of SDI-12 is

1 start bit
7 data bits, least significant bit transmitted first
1 parity bit, even parity
1 stop bit
I want to transmit an 24 bits of data i.e., 100001101011001010000100
which when arranged in frame looks like

start,1000011,P,stop, start,0101100,P,stop, start,1010000,P,stop, 
start,100_  _ ,P,stop
P->parity bit
the problem is
what data should I transmit in the last for bits i.e.,_  _ 
how should i know that the data to be sent is completed.
help me with any protocol to get an idea about
(how should i know that the data to be sent is completed.)
I'm attaching the code I've written
help me

CODE:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity serialtx is
generic (data_width : integer);
port ( clk,reset :in std_logic;
tx_data : in std_logic_vector(data_width-1 downto 0);
tx_out : out std_logic
);
end serialtx;
ARCHITECTURE behavioral of serialtx is
type ofstate is (IDLE, START_bit, STOP_bit);
signal state, nextstate : ofstate;
signal parity_bit,tx_enable : std_logic;
begin
process
variable count,p_val : integer:=0;
begin
if(clk'event and clk='1' and tx_enable='1')then
if(reset='1')then
tx_out<='0';
else
case state is
when IDLE =>
tx_out<='0';
nextstate<=START_bit;
when START_bit=>
count:=count+1;
if(count>=0 and count<7)then
for b in p_val to data_width-1 loop
tx_out<=tx_data(p_val);
end loop;
elsif(count=7)then
tx_out<=parity_bit;
p_val:=p_val+1;
elsif(count=8 )then
tx_out<='1';
nextstate<=STOP_bit;
count:=0;
end if;
when STOP_bit=>
--if--data to be sent is completed then
tx_out<='1';
tx_enable<='0';
--else
nextstate<=IDLE;
--end if;
end case;
end if;
end if;
end process;
end behavioral;

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