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Forum: FPGA, VHDL & Verilog using null range in my vhdl code


Author: Ravid G. (ravid_g)
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Hello,

I try to write my code in a generic fashion,
and this causes that there are cases in which I have signals with null 
range.
for example, if I have a signal :
SIGNAL a : std_logic_vector(X-1 downto 0);
then if X is 0, this is a null range vector, and this is ok.
when I use this way of writing in altera-quartus and modelsim, there is 
no problem and I simply get a null range warning.
but it appears that mentor-precision doesn't support this.

do you know if null range is a vhdl feature that must be supported?


Thanks
Ravid

Author: ehhh (Guest)
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X = 0
X-1 = -1...

Author: P. K. (pek)
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Maybe something like that could help:
signal M : integer range 15 downto 1;

Where "15" is just an example to have a complete statement.
Your vector then has a minimal length of 1. Smaller vectors (besides 
from an academic point of view) make not much sense, and you'll find a 
way to design around them.

Author: lkmiller (Guest)
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> but it appears that mentor-precision doesn't support this.
How do you come to that conclusion?

Author: Ravid (Guest)
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my mistake.
they do support it.

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