Forum: FPGA, VHDL & Verilog Isim Fatal Error

Author: dhootha adhi (Company: Student) (gollum)
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type comp is
    Rel :sfixed(7 downto -6);
    Img :sfixed(7 downto -6);
  end record;
type t11 is array (natural range<>) of comp;
type integer_type is array(natural range<>) of integer;
type array_name is array (natural range<>) of sfixed(7 downto -6);
type real_type is array(natural range<>) of real;

these are the types i used
I get this error every time i simulate.Please help me solving it

Author: P. K. (pek)
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Not a solution, but possibly a starting point:

Your error points to line #122. This is the statement "process(clock)". 
What I can see on a first glance: The only signal in your sensitivity 
list is never used inside your process. As a second item, you use only 
variables in this very process. No signal is ever assigned.

Maybe you didn't implement what you intended to? And maybe your error 
has to do with this fact?

Author: dhootha adhi (Company: Student) (gollum)
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Actual this test frame is supposed to be a function. I mean i should 
finally use it as a package.But i have to run this code and test whether 
the simulation results match with what i have (matlab code).That is why 
I was writing it as a module just to check the simulation results.

I used different variables than the signals like recevdframe instead of 
signal recvdframe..This is because I couldn't assign the default values 
of the signals to zero . recevdframe i want to have it a t11 type(array 
of a record). I didn't know how to initialise it to zero in the test 


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