hello , I'm a newbie on verilog/logic design. I wanna build a 3-bit counter by using D flip-flop and I wrote the program after reading the chapter from book "fundamental of logic design (by Charles H. Roth)". But the output of the counter has always been unknown state "xxx", not an expected value , ex. 000->001->010->....etc. I can't figure out what the problem is. can you tell me how to fix it if you have any information about solving the problem ? I attach my source file thank you
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/* : SRlatch2 ( s r ------------- ); */
module TX_SRlatch2_xo2(s,r, p, q); // STACK (4) Parameter
input s , r; // >Define i_INPUTS_via_HW_PIN | s_SET_FEEDHORN_Pv
,r_RESET_FEEDHORN_Pv
output p,q; // <Define o_OUTPUTS_via_HW_PIN_PUMP_01
/*-----------------*/
nand (p,s,q); // (x-X)--RC
/* PUFF that stuff -->THAT OUPUTS FEDD-BACK to inputs */
nand (q,p,r); // (X-x) -- RC CRISCROSS (X) interconnect
/* BUT SAY JUST thats LATTICE SOMKIE SYLE and win a TSHIRT */
endmodule
/*-----------------------------------------------*/
/*<<<<<<<<<<<<<<<<<< BLOCK
(|1.0|>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>><<*/
//######################################################################
#####
// ###################
/* : gated_DLatch(g,d,q); */
module gated_Holger_D_Latch(g, d, q); // STACK (3)Parameter
// the old Holger_oldDLatch
input g,d;
output q;
wire s1,r1,p; // create V-WIRE
nand (s1,d,g); // Transit V-WIRE
/* PUFF that stuff -->THAT OUPUTS FEDD-BACK to inputs */
nand (r1,~d,g); // not
/* TIP_PV */
/* @CALL : SRlatch2*/
/* -------------pPP-buff+88db*(PPROBE***********) */
SRlatch2_xo2 lcac_TRANSMITTER( s1 , r1 , p , q );// STACK (4)Parameter
// ## MACH X02 l
endmodule
//
#####################################-----------------------------------
----------
// : [gated_Holger_E_FLAP_D_Latch]
module gated_Holg_E_FLAP_D_Latch(g, d, q); // STACK (3)Parameter
// the #NEW eHolger_oldDLatch
input g,d; // >Define i_INPUTS_via_HW_PIN
output q; // <Define o_OUTPUTS_via_HW_PIN_PUMP_01
wire s1,r1,p; // VERTICAL V V V V V V V V
nand (s1,d,g);
nand (r1,~d,g); // D-fliPPP
/* TIP_PV */
/* @CALL : SRlatch2*/
/* -------------pPP-buff+88holger(PPROBE***********) */
SRlatch2_xo2 lcac_TRANSMITTER( s1 , r1 , p , q ); // STACK
(4)Parameter
// ## MACH X02 l
endmodule
/*-----------------------------------------------------*/
//######################## ENDE BLOCK
(|1.0|>>>#####################################################/*
*/
/*<<<<<<<<<<<<<<<<<< BLOCK
(|1.1|>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>><<*/
module edge_HOLGER__triggered_DD_flipFlop(clk, d, q);
input clk,d;
output q;
wire not_clk,p; // LOW 'Tick_Edge
not (not_clk , clk);
// Generate for XIX-USER
// create layout does> thOhe duplicate but
// now we generate an <OBI(H)(H)JECT> from
<edge_HOLGER_TriggertDD_ili| from
gated_Holg_D_Latch l1(not_clk,d,p); /*dup 2hD*/
gated_Holger_E_FLAP_Latch l2(clk ,p,q);
endmodule
//######################## ENDE BLOCK
(timing:00000????|1.1|>>>###############################################
######/*
// SO now we sit warm an toasty in the Lab to test that out.
// Later we can debug
// ??????????
/* Design a #{['Counter] using D Flip Flop --*/
/* ++++++VANILLA #0000---VECTOR */
// Design a #{['Counter] using D Flip Flop -----
// [ counter_by_3_dff( ); ]
/*-------------------------------------------------*/
module counter_by_3_dff( q, clk ); // ticks 2params
/*----------------------------------------------------------*/
input clk; //<< #'ticks_runticks_Master_ClockPort "D7"
/*-------< 'U >----------------------------------------------*/
/* Ticks a passing throW _-_-_-*/
/*-------------------------------------------------------------*/
output [2:0] q; // --'T>>++++/[4-'modulo [+###]03-(01)
wire feed_logic_1; // [ (|)_ } 'lsb
wire [2:0] d; // [ (|)_ (|)_ (|)_ } 'lbb
wire q0q1; // [ (|)_ } 'lsb
/*#### << ##############################################*/
// ASSIGN
/*########### << ##############################################*/
assign feed_logic_1 = ~clk; // FFFfffeddbaaaaakkk const !STORE
(++++)(|)_
// assign feed_logic_1 = 1; // const !STORE (++++)(|)_
// assign d = 3'b000; /// << #######
//// assign q = 3'b000; // << test#######
/*#### << ##############################################*/
/*#########################*/
/*+++++++++++++++++++++++++++++++++++++++++++++++++++++*/
xor (d[0],q[0],feed_logic_1); // <---neg_#'clk
xor (d[1],q[0],q[1]);
and (q0q1,q[0],q[1]);
xor (d[2],q[2],q0q1);
/*+++++++++++++++++++++++++++++++++++++++++++++++++++++*/
/* metager >>>>FIRS ROLLBACK develop tracker - for
RADA--fee-FEEED-HORRRN TRACHER*/
endmodule
/* FORTH TURN_KEY : [secret_()turn_key] */
/*<<<<<<<<<<<<<<<<<< main-engine-BLOCK
(|1.2|>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>><<*/
module turn_key( q, clk ); // ticks 2params
/*----------------------------------------------------------*/
//input clk; //<< #'ticks_runticks_Master_ClockPort "D7"
//output [2:0] q; // --'T>>++++/[4-'modulo [###]03-(01)
reg clk; //<< #'ticks_runticks_Master_ClockPort "D7"
reg [2:0] q; // --'T>>++++/[4-'modulo [###]03-(01)
/*######## KANOPE ###########*/
counter_by_3_dff cnt(q,clk);
/* metager ENGINE
GREEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEENNNNNNNNNNNNNNNNNNNNNNNNNN-->TRACHER
*/
/*#########################*/
endmodule
/*<<<<<<<<<<<<<<<<<< WEEnde main-engine-BLOCK
(|1.2|>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>><<*/
/*---************************************************--------*/
// test bench of the counter
module counter_by_3_dff_tb;
reg flipp_Master_clk, Master_clk;
wire [2:0] q; //
/*#########################*/
turn_key( q, Master_clk ); // ticks 2params
/*#########################*/
always begin /* Start_TSK_TASK_MODULE*/
#2 Master_clk = flipp_Master_clk; /*01000*/
// STEPER ENGINE
flipp_Master_clk <= ~ Master_clk; // copy to flip---):
//flipp_Master_clk = ~ Master_clk; // copy to flip---):
end
endmodule
THE SIMULATOR CRASHES because it runns forever in the node_module. Normal you an change it back. Runn All Tools on simulator. then you see, only flicker. Now it is Static.. Green. See Holger.
// test bench of the counter
module counter_by_3_dff_tb;
reg flipp_Master_clk, Master_clk;
wire [2:0] q; //
turn_key( q, Master_clk ); // ticks 2params
/*#########################*/
// alias --> counter_by_3_dff cnt(q,Master_clk);
/*------------------------*/
// counter_by_3_dff
always begin /* Start_TSK_TASK_MODULE*/
#2
flipp_Master_clk <= ~ Master_clk; // copy to flip---):
//flipp_Master_clk = ~ Master_clk; // copy to flip---):
Master_clk = flipp_Master_clk; /*01000*/
end
endmodule
no turnkey
/* ------------------------------------------------------------------------ ----------------*/ // CPLD FPGA BITZELLEN MODULATION mit NAMEN zu DOKU und IDENT- HANDLING AND .###Anschluss .. // Lattice CPD MachX02 MachX0 //PROZESS VISUALISIERUNG PROZESS VARIABEN MANAGEMENT ...
hi , Holger Is the file you attached the same as my file ? did you modify any part of original source file? I check your file but it seems be the same sorry , I don't understand what you mean can you explain that further ? I use Xilix ISE for development ,and Isim for simulation thank you so much
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