EmbDev.net

Forum: FPGA, VHDL & Verilog numeric_std, std_logic_vector to integer


Author: A. S. (aleksazr)
Posted on:

Rate this post
0 useful
not useful
code snipets:

use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity TEST is port (
    addr : in integer range 0 to 31;
end TEST;

component TEST port (
    addr : in integer range 0 to 31;
end component;



DBUS : inout std_logic_vector(15 downto 0);

Inst_TEST: TEST port map (
    addr => to_integer(unsigned(DBUS(4 downto 0))),
);

This is where I get the ISE error:
Actual, ParameterAssocOp, associated with
Formal Signal, Signal 'addr', is not a Signal. (LRM 2.1.1)


What am I doing wrong here?

Author: P. K. (pek)
Posted on:

Rate this post
0 useful
not useful
> What am I doing wrong here?

Mapping "inout" to "in" port?

Author: Lothar Miller (lkmiller) (Moderator)
Posted on:

Rate this post
0 useful
not useful
Try it with a local signal:
:
:

DBUS : inout std_logic_vector(15 downto 0);
addrhelp : integer range 0 to 31;



addrhelp <= to_integer(unsigned(DBUS(4 downto 0)));

Inst_TEST: TEST port map (
    addr => addrhelp
);

In this way no function or procedure is called within the port 
assignment...

Author: A. S. (aleksazr)
Posted on:

Rate this post
0 useful
not useful
Peter K. wrote:
> Mapping "inout" to "in" port?

No, that wasn't the problem...

Author: Lothar Miller (lkmiller) (Moderator)
Posted on:

Rate this post
0 useful
not useful
And what was the problem?

Author: A. S. (aleksazr)
Posted on:

Rate this post
0 useful
not useful
Lothar Miller wrote:
> In this way no function or procedure is called within the port
> assignment...

Thats it, thanks.



"You can't put the conversion right in the port mapping."
http://forums.xilinx.com/t5/Synthesis/numeric-std-...

Author: A. S. (aleksazr)
Posted on:

Rate this post
0 useful
not useful
Lothar Miller wrote:
> And what was the problem?

I intended to reply to both you and Peter
at the same time, but got interrupted in between.

Reply

Entering an e-mail address is optional. If you want to receive reply notifications by e-mail, please log in.

Rules — please read before posting

  • Post long source code as attachment, not in the text
  • Posting advertisements is forbidden.

Formatting options

  • [c]C code[/c]
  • [avrasm]AVR assembler code[/avrasm]
  • [vhdl]VHDL code[/vhdl]
  • [code]code in other languages, ASCII drawings[/code]
  • [math]formula (LaTeX syntax)[/math]




Bild automatisch verkleinern, falls nötig
Note: the original post is older than 6 months. Please don't ask any new questions in this thread, but start a new one.