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Forum: FPGA, VHDL & Verilog Generation of the clock of having a programmable data rate from 64bps to 30Mbps


Author: anjali komalapati (Company: iqi labs) (anjali)
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Hi, can any1 help me writing a program for generation of Clock having 
programmable data rate of 64bps to 30 Mbps by using DCM(Digital Clock 
Manager).
 Iam very new for this concept and i don't have any idea on this please 
help me.
 thanks in advance.

Author: Lothar Miller (lkmiller) (Moderator)
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> by using DCM (Digital Clock Manager).
Which DCM?

> programmable data rate of 64bps to 30 Mbps
Out of which clock frequency?

To keep things short: tell AS MUCH AS POSSIBLE about your system and 
what you want to get helpful answers.

Author: PittyJ (Guest)
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