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Forum: FPGA, VHDL & Verilog decoder (bcd to 7segments)


von bonildo (Guest)


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Hi guys, I'm new in VHDL and would be glad if anyone could help me with 
my bcd-7segments decoder. I dont know why its not compiling

von P. K. (pek)


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Does it work, if you make the last assignment unconditional? And, of 
course no semicolons between the elses.
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else HEX0 <= "0000000" when a="1000"
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else HEX0 <= "0010000"; --when a="1001"

von Lothar M. (Company: Titel) (lkmiller) (Moderator)


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bonildo wrote:
> I dont know why its not compiling
What error message do you get?

Peter K. wrote:
> And, of course no semicolons between the elses.
I also assume the semicolons to be the problem.

> Does it work, if you make the last assignment unconditional?
Thats not the actual problem, but not doing this will cause the 
synthesizer to generate a latch, because only 10 out of the 6561 
possible values of a 4 bit std_logic_vector are used (4 digit with each 
9 values {UX01ZWLH-} = 9*9*9*9 = 6561). This vast amount of values is of 
interest mainly for simulation, but also in real hardware a 4 bit vector 
can have 16 values, and therefore there must be a kind of "memory" for 
the "last valid" value, if a is greater than 9.

I would change the code so, that if there is a input value greater than 
9 a "-" is displayed:
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else HEX0 <= "0000000" when a="1000"  --  8
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else HEX0 <= "0010000" when a="1001"  --  9
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else HEX0 <= "0111111";               --  -

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