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Forum: FPGA, VHDL & Verilog Help with instruction fetch unit in VHDL


Author: Shay Golan (Guest)
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Hello,

In cpu architecture course, we were tasked with building a single cycle 
MIPS cpu.

after writing the entire architecture and performing multiple test 
benches we wrote the architecture to an fpga board and... it didn't 
work.

Examining things closely, we found out there's something wrong with our 
instruction fetch. mainly, the PC can't advance to the next instruction 
address. I wrote down a simple entity with 2 components - a 32 bits 
register and an adder. the register outputs data (program address) to 
the adder. the adder performs a "+4" on the address and sends it back to 
the PC.

Simple, isn't it?

But it's not working, for some reason - when i simulate this unit it 
only has junk on it's bus (XXXXXXXX on modelsim). I can't find the 
problem and i'm desperate. i have attached all the relevant files. can 
someone find what the problem is?

thank you,

Shay

Author: Lothar Miller (lkmiller) (Moderator)
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Shay Golan wrote:
> after writing the entire architecture and performing multiple test
> benches
With success?
Was the fetch unit in question also tested?

> we wrote the architecture to an fpga board and... it didn't work.
How many clocks do you have in the whole design?

> Examining things closely, we found out there's something wrong with our
> instruction fetch. mainly, the PC can't advance to the next instruction
> address. I wrote down a simple entity with 2 components - a 32 bits
> register and an adder. the register outputs data (program address) to
> the adder. the adder performs a "+4" on the address and sends it back to
> the PC.
>
> Simple, isn't it?
The task is fairly simple, your solution is very complicated.
Why using a bunch of files for this simple task?
Why implementing an adder and discarding one bit?


> But it's not working, for some reason - when i simulate this unit it
> only has junk on it's bus (XXXXXXXX on modelsim). I can't find the
> problem and i'm desperate.
X means there is more then only one driver on this signal..
And you cannot initialize this here with 0
   signal NextPC :std_logic_vector(N-1 downto 0):=zeroes;
and here:
    dataOut:out std_logic_vector(N-1 downto 0):=zeroes
when it is also at the same time an output with an undefined value here:
    signal Q_tmp: std_logic_vector(N-1 downto 0);
    :
    dataOut <= Q_tmp;

This must be the only place to be initialized:
    signal Q_tmp: std_logic_vector(N-1 downto 0) := (others=>'0');

It took me about 2 minutes to locate this fairly common error because i 
had to dig around in 3 files. Would the complete code (a simple 
registered adder) had been located in 1 file, the you would have seen 
the problem yourself...

> i have attached all the relevant files. can
> someone find what the problem is?
This is not the testbench you used, is it?
Because you will not be able to compile it:
    process      -- Start of test bench run:
    begin                          
    clear <= '0';
    wait for 300 ns; 
               --------- a endless process?

end TB;

Author: Shay Golan (Guest)
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Hi lothar,

thanks for the extensive answer, as for your questions:

the fetch unit was not test benched, because it wasn't designed as a 
separate entity. i came back to simulate it once i discovered the 
problem lay in that area.

We use a single clock in the design.

the adder we use is the same adder from inside the alu we implemented 
for the cpu core, i just used it and inserted a signal which equals 
four. I'm using a bunch of files because our implementation for the core 
is structural. inside the core entity (which i didn't include in the 
files i attached for the reason of keeping my question simple) there's a 
data flow from the register to the adder and then to another adder (in 
case there's a branch), i chose to implement it that way because it 
seemed to me the most modular way to do it.

i will try your solution and see if it works. i'll come back with an 
answer.

anyway, thanks a lot for the help - much appericiated! :)

Shay

Author: Shay (Guest)
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Thanks! It's working now!

Author: otto (Guest)
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>In cpu architecture course, we were tasked with building a single cycle
>MIPS cpu.

How much time do you get for this task?

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