# Forum: FPGA, VHDL & Verilog Vhdl implementation of Reed Solomon encoder

 Author: Ravi Pratap Singh (Company: Student) (ravipratap) Posted on: 2012-05-30 20:01
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In the above block Diagram, we are using Galois arithmetic to form an
encoder. here the field generator polynomial(p(x)) and code generator
polynomial(g(x))are taken as follows,
We have used p(x)= x4+x+1
and
g(x)=(x+1)(x+2)(x+4)(x+8)
= x^4+15x^3+3x^2+x+12
The message polynomial is taken as:
M(x) = x^14 +2x^13 +3x^12 +4x^11 +5x^10 +6x^9 +7x^8 +8x^7 +9x^6 +10x^5
+11x^4 + 12x^3 +13x^2 +14x +15

Then this is multiplied by x4  to give:

x^18 + 2x^17 + 3x^16 + 4x^15 + 5x^14 + 6x^13 +7x^12 +8x^11 +9x^10 +10x^9
+11x^8 +12x^7 +13x^6 +14x^5 +15x^4
to allow for spacing for parity symbols.

This is then divided by (x+1)(x+2)(x+4)(x+8) to produce the parity
symbols
as remainder.
So can you tell me what will be the remainder that we will get here!!

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