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Forum: FPGA, VHDL & Verilog Carrier Generator


Author: Pratyush Anand (pratyush23)
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i wish to design a digital carrier generator, the diagram of which i am 
attaching herein..
for the same i have used the following building blocks:

1> 2:1 Mux(multibit)
2> Digital Integrator (multibit)
3> A Delta function block (unit impulse function)
4> A Clock
5> A 4x4 bit multiplier, wherein only the first 4 bits of the product 
have been considered.

I ran the code and it synthesized perfectly well..but on generation of 
test bench waveform, the output ports were undefined..

i m unable to figure out as to how to supply the values to the building 
blocks through the signals...

Please suggest the required changes/errors..

Thanks.

Author: P. K. (pek)
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Difficult to say, a number of reasons may be the source:

- Testbench: Are all your inputs defined?
- Non-existing instances (e.g. is your multiplier instantiated?)
- Missing definition of initial values (ever propagating)

Just display the intermediate signals in your waveview and track the 
undefined signal(s) down to the root cause. Maybe (if existing) read the 
simulator compilation warnings and try to avoid them.

Author: Lothar Miller (lkmiller) (Moderator)
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> I ran the code and it synthesized perfectly well..
Are you sure?
This code IS ABSOLUTELY NOT synthesizeable!
  for i in 1 to 10 loop     
    clock_xhdl0 <= '1';
    wait for 100 ns;
    clock_xhdl0 <= NOT(clock_xhdl0);
    wait for 100 ns;
  end loop;

> but on generation of test bench waveform, the output ports
> were undefined..
I cannot see a testbench in your code. A testbench entity has NO ports. 
But each of your modules has ports...

BTW:
> A 4x4 bit multiplier
A multiplier is in VHDL usually done like this
   a <= b*c;

BTW:
Why using a
   GENERIC (  WIDTH  : INTEGER := 4 );
in your multiplexer, when you later use a fixed vector to extend /a/:
   c <= ("000" & a) WHEN (sel = '1') ELSE    b;

What, if i would take your generic code and write
   GENERIC (  WIDTH  : INTEGER := 6 );

Author: Pratyush Anand (pratyush23)
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I am unable to update the 4-bit signals(a,b and c) which are used 
interchangeably as input and output in the connecting blocks.
Eg. The signal c which is the output of mux is also the input of the 1st 
integrator. Since the values are not being updated, as a result the 
signals are showing as undefined in the tbw simulation.

Author: P. K. (pek)
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Pratyush Anand wrote:
> I am unable to update the 4-bit signals(a,b and c) which are used
> interchangeably as input and output in the connecting blocks.
> Eg. The signal c which is the output of mux is also the input of the 1st
> integrator.

You do not need to update c by hand, this is the task of your 
"mux_2to1".

> Since the values are not being updated, as a result the
> signals are showing as undefined in the tbw simulation.

You have to find out why. Observe the signal(s) that influence your 
undefined one, e.g. c, in the waveview. In that case, observe a,b and 
sel.

Do so recursively with those of the 3 signals (a,b and sel), which are 
undefined, until you have found the origin of undefinedness. This will 
lead to the earlier posted possible reasons of problems:

- Testbench (not posted...): Are all your inputs defined?
- Non-existing instances (e.g. is your multiplier instantiated?)
- Missing definition of initial values (ever propagating)

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