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Forum: FPGA, VHDL & Verilog writing a vhdl or verilog program for the ddr3 power up initilization


Author: anjali komalapati (Company: iqi labs) (anjali)
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Hi, i have attatched on file in which there is a timing diagram and a 
flow chart for ddr3 power up initialization, can any1 help me how to 
start writing a vhdl or verilog code for this. please.
Thanks in advance.

Author: PittyJ (Guest)
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There are 24 steps described in the PDF, which are needed for 
initialization.
Write a state machine, which covers the 24 steps and assign the correct 
values for the ports at each state.

Author: anjali komalapati (Company: iqi labs) (anjali)
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ya in that i need to start wring from Reset which is from 4th step. but 
iam unable to start it how to write iam a very new for this so please 
can u provide me.

Author: P. K. (pek)
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Usually, these kind of initialisation steps are handled by the DDR(3) 
controller IP. Are you intending to write your own memory controller?

Writing your own DDR controller is very uncommon and usually only done 
when you have very special requirements (and probably happening more 
frequently on an own IC than on an FPGA), good skills in that area are 
required.

Nothing for someone who claims to be "very new for this". I suggest you 
start using a DDR controller IP, or if you want really to do it by 
yourself, with a "hello world" kind of FSM (e.g. adressing an LEDS, SPI, 
etc. to get some idea about this).

Good luck.

Author: anjali komalapati (Company: iqi labs) (anjali)
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Actually i need to interface a ddr3 memory to an virtex6 fpga so in that 
this power up initialization is one of the part so i need to develop 
that so for making to start, what is the process and how to start.

Author: PittyJ (Guest)
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What I'm wondering about: you are working at iqi labs.

iqi labs has (taken from their homepage)
Technical expertise counts through engineers, averaging 15 years of 
experience in VHDL

Why don't you ask your collegues about writing a state machine?
State machines are very basic, and every VHDL engineer should know about 
it.

Author: King Harkan of Norway the Forth (Guest)
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I guess this is because, there are 5 students having 3 years of 
experience each. 5x3 = 15!

Seriously, the virtex6 requires nothing else than the usage of the 
MIG-based DDR-3 controller core.

Author: anjali komalapati (Company: iqi labs) (anjali)
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Actually i generated the code by using MIG long back and it is working. 
But again now here there is a problem with something so i need to write 
code for power up initialization so that is why i was searching and 
asking for the help.

Author: klar. (Guest)
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> Actually i generated the code by using MIG long back and it is working.

you posted on 2012-05-08 06:52
> HI, i have generated the code for ddr3 interfacing with virtex6 fpga but
> iam unable to understand is that right or wrong.

A mircale must have happend...

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