# Forum: FPGA, VHDL & Verilog shift left or shift right

 Author: deepak singh (dksagra) Posted on: 2012-05-05 15:32

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hi
how can i shift left or shift right the data in vhdl.
let i have x
constant x:std_logic_vector(7 downto 0):"01000101";

how can i use the command sla sra for this particular x...

thanks and regards

 Author: blub (Guest) Posted on: 2012-05-05 15:35

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You can map the bits 0,1,2,3, n-1    (leave out the last bit)
to a new vector 1,2,3,4,...,n  and concatenate this vector with a
leading "0"

 Author: deepak singh (dksagra) Posted on: 2012-05-05 16:10

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thanks for the reply..
but really i didnt get you..
if possible for you then please can you help me with one example..

thanks and regards

 Author: Lothar Miller (lkmiller) (Moderator) Posted on: 2012-05-05 16:22

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deepak singh wrote:
> how can i use the command sla sra for this particular x...
You cannot use SLA and SRA for std_logic_vectors.
SLA and SRA are defined for bitvectors only.

> how can i shift left or shift right the data in vhdl.
> let i have x
>   constant x:std_logic_vector(7 downto 0):"01000101";
You cannot shift a constant.

So: what do you want to do?

This will work for a one bit shift:
  signal x:std_logic_vector(7 downto 0):"01000101"; -- arithmetic right shift x <= x(7) & x(7 downto 1); -- arithmetic left shift x <= x(6 downto 0) & '0'; -- logic right shift x <= '0' & x(7 downto 1); -- logic left shift x <= x(6 downto 0) & '0'; 

 Author: deepak singh (dksagra) Posted on: 2012-05-05 16:38

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thanks..

you are exceptionally master piece, not because you have solved my
problem..

i have gone through your website..you did fantastic work in VHDL..
its great you are spreading you knowledge to ppls like me who is no
where stand in front of you..

thanks and regards,

 Author: deepak singh (dksagra) Posted on: 2012-05-05 17:06

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Dear Miller,
what if i have a matrix
program as follows

library IEEE
...
...

Package matrix_types Is
Type matrix_4x1 Is Array (1 to 4) Of std_logic_vector (7 downto  0);
Type matrix_1x4 Is Array (1 to 4) Of std_logic_vector (7 downto  0);
Type matrix_4x4 Is Array (1 to 4, 1 to 4) Of std_logic_vector (7 downto
0);
End Package matrix_types ;
...
...
architecture.......
begin
.....
process
.......

Variable x : matrix_4x1 :=
("000000100",
"0000000000",
"0011110000",
"0010110001");

begin

now i have to shift left or shift right EACH ROW of variable x TWICE or
THRICE etc.

Thanks and Best Regards,

 Author: deepak singh (dksagra) Posted on: 2012-05-06 10:48

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Dear Miller,

Thanks and Regards

 Author: Lothar Miller (lkmiller) (Moderator) Posted on: 2012-05-07 08:35

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> now i have to shift left or shift right EACH ROW of variable x TWICE or
> THRICE etc.
And from where comes the information about the shift count? Is that a
constant? A "variable" shifter (lets say shift a byte by -7..+7) is not
that simple! Because that results in a fairly BIG multiplexer...

Lets do it this way:
1. you show what you have,
2. you say what you want to achieve,
3. you report whats the problem with your description,
and then maybe
4. someone can help you...

 Author: Jack (Guest) Posted on: 2016-01-29 18:13

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How do design a shift left circuit manually where the inputs a, which is
an 8bit signal to be shifted, and ctrl which is a 3 bit signal
specifying the amount to be shifted, Both are std_logic_vector type.
using concurrent signal assignment, derive this circuit.

Hope you can help me. I really need help.

 Author: P. K. (pek) Posted on: 2016-02-03 08:45

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Sounds like a big multiplexer. As it is required to be done using
concurrent signal assignment it looks like

 result <= shift0 when sel = "000" else ... shift6 when sel = "110" else shift7; 

By the way: Maybe it's not a good idea to resurrect 4 year old dead
threads. Just do a new one.

: Edited by User

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