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Forum: FPGA, VHDL & Verilog for loop in vhdl


Author: priyanka kalode (Company: student) (abc24)
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hi...

i want to know whether for loop in vhdl is synthesizable or not???

Author: Marius Wensing (mw1987)
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Yes, it is synthesizable. But it will create parallel logic.

Best regards,
Marius

Author: priyanka kalode (Company: student) (abc24)
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Marius Wensing wrote:
> Yes, it is synthesizable. But it will create parallel logic.
>
> Best regards,
> Marius

so what it means parallel logic?

dose it creats any problem in design later?

Author: Lothar Miller (lkmiller) (Moderator)
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> i want to know whether for loop in vhdl is synthesizable or not???
Yes it is, but it will produce completely different results than a 
loop in any software programming language!

> so what it means parallel logic?
In software a loop will be processed one loop after the other, in 
hardware ALL of the loops will exist next to each other. And the whole 
loop will be executed the very same time!

> dose it creats any problem in design later?
Try it with a short and simple sample code...
Or: show your code...

Author: priyanka kalode (Company: student) (abc24)
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but there is any change in logic if we implement it with help of for 
loop??

Author: Andreas Schwarz (andreas) (Admin) Flattr this
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What logic? A change compared to what?

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