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Forum: FPGA, VHDL & Verilog Array Multiplier


Author: O'Shea (Guest)
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Hi there, I'm having trouble getting this array multiplier working 
correctly and I can't figure out what the problem is.  If someone could 
just glance at my code it'd really help
module array_multiplier
(
  output [15:0]P,
  input [7:0]A,
  input [7:0]B
);
wire [55:0]Sum;
wire [6:0]Cout;

assign P[0] = A[0] & B[0];

//Level 1
ripple_carry_adder RCA1(Cout[0], Sum[7:0],   {1'b0, B[0] & A[7:1]}, B[1] & A[7:0],1'b0);
assign P[1] = Sum[0];

//Level 2
ripple_carry_adder RCA2(Cout[1], Sum[15:8],  {Cout[0], Sum[7:1]},   B[2] & A[7:0],1'b0);
assign P[2] = Sum[8];

//repeat....

//Level 7 (last level)
ripple_carry_adder RCA7(Cout[6], Sum[55:48], {Cout[5], Sum[47:41]}, B[7] & A[7:0],1'b0);
assign P[7] = Sum[48];

assign P[8] = Sum[49];
assign P[9] = Sum[50];
assign P[10]= Sum[51];
assign P[11]= Sum[52];
assign P[12]= Sum[53];
assign P[13]= Sum[54];
assign P[14]= Sum[55];
assign P[15]= Cout[6];

//module
module ripple_carry_adder
(
  output Cout, 
  output [7:0]Sum,  
  input [7:0]A, 
  input [7:0]B, 
  input Cin
);

Author: Lothar Miller (lkmiller) (Moderator)
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O'Shea wrote:
> I'm having trouble getting this array multiplier working correctly
And what kind of trouble is that?
Are there any errors or warnings?

Author: O'Shea (Guest)
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Sorry I should have been more specific, it compiles okay it just doesn't 
function properly.  When both A[0] and B[0] are 1's then it produces a 
number with a 1 in P[0] like it should.  However, when either A[0] and 
B[0] are not 1 it produces zero in P[15:0].  In my vector file I have 
Sum as a variable to watch but it says that it cannot find any instances 
of Sum (any of them, it gives me many many warnings), which is 
unfortunate because I could use that to do a little debugging

Author: Duke Scarring (Guest)
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> Sorry I should have been more specific, it compiles okay it just doesn't
function properly.
Where did you check the function? In simulation or on hardware?

Duke

Author: O'Shea (Guest)
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Simulation

Author: O'Shea (Guest)
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Bump

Author: User (Guest)
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Hello, maybe someone know how to implement divider in VHDL when i have 
just Multiplier ?

thanks.

Author: Lothar Miller (lkmiller) (Moderator)
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Why does everybody add his/hers NEW question to and ancient post?
With a new question start a new thread, pls.!

And there you can write, whether you want the division for synthesis or 
"only" for simulation. And maybe also, which toolchain from which 
supplier you use. And all the necessary additional information that may 
be helpful (word width, speed, precision...)...

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