EmbDev.net

Forum: FPGA, VHDL & Verilog Signals vs Variables


Author: Omar Saif (omar-saif)
Posted on:

Rate this post
0 useful
not useful
Dear All,

Can i Ask, how signals and variables be represented in a hardware?; (I 
mean the difference between them in a hardware point of view).
And what is the difference between them in a clocked process?

Another question please, What is the difference between the 
combinational and sequential process?

thanks in advance.

Author: user (Guest)
Posted on:

Rate this post
0 useful
not useful
when you describe hardware with vhdl, you normaly do not neet to use 
variables, use signals.

Author: Lothar Miller (lkmiller) (Moderator)
Posted on:

Rate this post
0 useful
not useful
Omar Saif wrote:
> Can i Ask, how signals and variables be represented in a hardware?;
Yes you can.

> (I mean the difference between them in a hardware point of view).
Is there any difference?
Or: whats the difference between signals?
One signal may be just a wire (or a connection), the other signal may be 
a flipflop, a third signal may be a complete memory block.

And a variable can be all of that too.

So: there is absolutely no difference between signals and variables in 
hardware!

> And what is the difference between them in a clocked process?
You will not see a difference in hardware.

> Another question please, What is the difference between the
> combinational and sequential process?
Thats a very academic question.
In reality a combinational and a sequential process can look the same.
Its like you are asking: whats the difference between a vehicle and a 
car?
A vehicle can be a car...

Try this german thread with google translator
Beitrag "Variable vs Signal"
Maybe its working and you can get some information out of it...

Author: Omar Saif (omar-saif)
Posted on:

Rate this post
0 useful
not useful
thanks so much, Lothar Miller, for your reply that i found it was 
helpful.

Another question please,

When i assign a value to a signal, is there a time delay to get 
assigned? and if so, this time delay can be represented by a buffer in a 
hardware?

Author: Lothar Miller (lkmiller) (Moderator)
Posted on:

Rate this post
0 useful
not useful
> When i assign a value to a signal, is there a time delay to get assigned?
No, because at first a signal is represented by nothing, its only a word 
in a text editor. And thats the way the simulator looks at it: just a 
word, no delays, no gliteches, no spikes or whatsoever...

> and if so, this time delay can be represented by a buffer in a hardware?
When you implement/synthesize this "signal" it will become a wire. Or it 
will become a flipflop, or it will become something else. And then /of 
course/ you will get all the timing effects like delays or latency.
But that is not due to the signal is a signal, its due to the signal 
is transported to reality...

Exactly the same can/will happen to variables! At first there is 
(virtually) no delay. When they are implemented on hardware they will 
get delays or latency. And as with signals on real hardware you can see 
glitches, spikes and all the other nasty things.

Reply

Entering an e-mail address is optional. If you want to receive reply notifications by e-mail, please log in.

Rules — please read before posting

  • Post long source code as attachment, not in the text
  • Posting advertisements is forbidden.

Formatting options

  • [c]C code[/c]
  • [avrasm]AVR assembler code[/avrasm]
  • [vhdl]VHDL code[/vhdl]
  • [code]code in other languages, ASCII drawings[/code]
  • [math]formula (LaTeX syntax)[/math]




Bild automatisch verkleinern, falls nötig
Note: the original post is older than 6 months. Please don't ask any new questions in this thread, but start a new one.