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Forum: FPGA, VHDL & Verilog Problem with clock in FPGA


Author: Vineela Tangudu (Company: Efftronics Sys Pvt Ltd) (vineela)
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Is there any relation ship between clock and output? Actually i'm using 
PLL to generate clock of any frequency(1.5 to 350MHz) and using that 
clock as a reference for the code.

If I use sclk freq of 14MHz and i'm changing the upperlimit of count 
value (indicated using comments in the code) then the real output is not 
as post synthesis simulated output.

ie it works when count="0001000100010111000000" and it is not working 
when count ="0000111110001001010001" in the if condition.


please help....

Author: Lothar Miller (lkmiller) (Moderator)
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> ie it works when count="0001000100010111000000" and it is not working
> when count ="0000111110001001010001" in the if condition.
Why do you not count with integers? Then you can write
        if(count>0 and count<49) then  ...
instead of
        if(count>"000000000000000000000" and count<"000000000000000110001") then ...


You have a VERY UNUSUAL way to describe clocked processes:
process(temp1,reset,templock)
begin
    if(reset='1' and templock='1') then
        if(count>"000000000000000000000" and count<"000000000000000110001") then
            if falling_edge(temp1) then  --- Huh, a clock. Here?

Additionally you muddle up combinational and clocked processes. And you 
also have two clocks in one process:
process(temp1,data,intaddr,reset,templock)
begin
    if(reset='1' and templock='1') then               -- first combinational
        if(count>"000000000000000000000" and count<"000000000000000110001") then
            if rising_edge(temp1) then                -- then a clock
                :
            end if;
        elsif(count = "000000000000000110001") then   -- then combinational
            if rising_edge(temp1) then                -- and again a clock
                :
                intaddr<=intaddr+1;
            end if;
        else                                          -- further on combinational
            :
            data<=LETTER_DB(conv_integer(intaddr));            
        end if;        
    else                                             
        intaddr <= "0000000"; 
        :
    end if;
end process;
I urge you to have a close look how others are doing it. Although your 
description may work (because synthesizers get better each day), you 
will NOT see this style in any book!

>  if rising_edge(temp1) then
>  if falling_edge(temp1) then
In a synchronous design there is only 1 clock. Thats the "one and only" 
system clock. And the whole design uses the same edge of this clock. 
temp1 sounds not like a system clock...  :-/

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