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Forum: FPGA, VHDL & Verilog help needed in top level creation


Author: sreekanth beee (sreekanthbv)
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hi,

i am very new to vhdl coding. so, i  need some help in creating the top 
level for two sub modules. i have written the following code for it.

------------------------------------------------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_unsigned.ALL;
use ieee.numeric_std.all;

entity system is
Port ( clk : in STD_LOGIC;
       reset : in STD_LOGIC;
       tdata_in : in std_logic_vector(7 downto 0);
       tdata_out : out std_logic_vector(7 downto 0)
       );
end system;

architecture Behavioral of system is

component InternalADC is
    port (
        reset     : in  std_logic;
        clk       : in  std_logic;
        wr        : in  std_logic;
        rd        : in  std_logic;
        addr      : in  std_logic_vector(7 downto 0);
        data_in   : in  std_logic_vector(7 downto 0);
        data_out  : out std_logic_vector(7 downto 0);
        miso      : in  std_logic;
        next_mosi : out std_logic;
        next_sck  : out std_logic;
        cen       : out std_logic;
        EOC       : in  std_logic;
        PowDownAD : out std_logic
    );
end component;

component afsk is
    Port (
            Clk : in  STD_LOGIC;
            reset : in  STD_LOGIC;
          bfs1 : in std_logic_vector(19 downto 0);
            bdata_in : in  std_logic_vector (7 downto 0);
            bdata_out : out  STD_LOGIC
        );
end component;


signal bfs1 : std_logic_vector (19 downto 0);
signal data_int : std_logic_vector (7 downto 0);

begin

a : InternalADC PORT MAP (clk, reset, wr, rd, addr, miso, next_mosi, 
next_sck, cen, EOC, PowDownAD,
                           data_in => tdata_in,
                           data_out => data_int);

b : afsk PORT MAP ( bfs1, clk, reset, data_int, bdata_out => tdata_out);


end;
------------------------------------------------------------------------ 
-
------------------------------------------------------------------------ 
-

but it gives me the following errors when i simulate it...
-----------------------------------------------------------

# ** Error: C:/Actelprj/afsk_top/hdl/top.vhd(52): (vcom-1028) Formal 
"data_in" has already been associated in a positional association.
# ** Error: C:/Actelprj/afsk_top/hdl/top.vhd(53): (vcom-1028) Formal 
"data_out" has already been associated in a positional association.
# ** Error: C:/Actelprj/afsk_top/hdl/top.vhd(53): VHDL Compiler exiting
# ** Error: C:/Actel/Libero_v9.1/Model/win32acoem/vcom failed.
# Error in macro ./run.do line 14

please help me with this problem..

Author: Lothar Miller (lkmiller) (Moderator)
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> please help me with this problem..
First you start with positional association, then you turn over to 
direct association:
   a : InternalADC PORT MAP (clk, reset, wr, rd, addr, miso, next_mosi, next_sck, cen, EOC, PowDownAD,
                           data_in => tdata_in,
                           data_out => data_int);


Try it with using only direct assigning internal signals
a : InternalADC PORT MAP (clk => clk, 
                          reset => reset, 
                          wr => the_write_signal, 
                          rd => your_read_signal, 
                          addr => address, 
                           :
                           :
                          data_in => tdata_in,
                          data_out => data_int);

BTW: here you muddeld up clk and reset.
component InternalADC is
    port (
        reset     : in  std_logic; -- first reset
        clk       : in  std_logic; -- then clk
        wr        : in  std_logic;
        rd        : in  std_logic;
        :
        :

              --  first clk then reset
a : InternalADC PORT MAP (clk, reset, wr, rd, ...... );
That would lead to funny effects...
And this also:
[vdhl]
USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_unsigned.ALL;
use ieee.numeric_std.all;
[/vdhl]
You MUST use either the old ones:
[vdhl]
USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_unsigned.ALL;
[/vhdl]
Or much better the:
[vhdl]
use ieee.numeric_std.all;
[/vdhl]
But never ever all of them together, because then you will have some 
datatytes declared a little bit different, and some functions wre 
declared in both of them and so the synthesizer will not know wich 
conversions to use...

Author: sreekanth beee (sreekanthbv)
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Hello Mr.Lothar Miller,

Firstly thanks for your response..
for direct assignment of the internal signals, i don't have the inputs 
for "wr" and "rd" and rest of the internal signals in the top level 
entity.

entity system is
Port ( clk : in STD_LOGIC;
       reset : in STD_LOGIC;
       tdata_in : in std_logic_vector(7 downto 0);
       tdata_out : out std_logic_vector(7 downto 0)
       );
end system;

 so, i have a doubt that how to deal in this situation.

Author: Lothar Miller (lkmiller) (Moderator)
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> i don't have the inputs for "wr" and "rd" and rest of the internal
> signals in the top level entity.
> so, i have a doubt that how to deal in this situation.
You will have to implement those signals. Because thats obviously the 
only way you can the component InternalADC...

Author: Duke Scarring (Guest)
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> i don't have the inputs
> for "wr" and "rd" and rest of the internal signals in the top level
> entity.
Ports of type output you can leave 'open'. For input ports you can use 
constants:
dac_instance: InternalADC
    port map (
        reset    => reset,      -- : in  std_logic;
        clk      => clk,        -- : in  std_logic;
        wr       => '0',        -- : in  std_logic;
        rd       => '1',        -- : in  std_logic;
        addr     => "00000000", -- : in  std_logic_vector(7 downto 0);
        data_in  => "00000000", -- : in  std_logic_vector(7 downto 0);
        data_out => open,       -- : out std_logic_vector(7 downto 0);
        ...
    );

Duke

Author: Lothar Miller (lkmiller) (Moderator)
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Duke Scarring wrote:
> Ports of type output you can leave 'open'. For input ports you can use
> constants:
Right, but then the ignored outputs MUST be of no use to the design. And 
the component also MUST be able to work without those signals. I cannot 
believe that a module with wr and rd signals don't use them...

Author: sreekanth beee (sreekanthbv)
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hi,

thanks for your valuable suggestions... if one of my sub module contains 
a generic declaration in its entity.. should i have to declare and 
instantiate the generics in the top level as well? if so can any one 
guide me how to do it with an example...

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