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Forum: FPGA, VHDL & Verilog Handling float values


Author: Galen gong (Company: UM biomed lab) (phantomonkey)
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I have a function that assigns distance based off an ascii value.

module assign_distance(clk, command_ready, distance, homesw, d, d_hex);
input clk;
input command_ready;
input [7:0]distance;
input homesw;

output [7:0]d;
output [6:0]d_hex;

reg [7:0]d;
reg [6:0]d_hex;

initial begin
  d=8'b00000000;
  d_hex=7'b1000000;
end


always @(posedge clk)
begin
  if (command_ready==1) begin
    if ((distance==8'b00110000)|(distance==0)) begin // ASCII for "0"
      d=8'b00000000;
      d_hex=7'b1000000;  // 7-segment display "0"
    end else if (distance==8'b00110001) begin // ASCII for "1"
      d=8'b00000001;
      d_hex=7'b1111001; // 7-segment display "1"
    end else if (distance==8'b00110010) begin // ASCII for "2"
      d=8'b00000010;
      d_hex=7'b0100100; // 7-segment display "2"
    end else if (distance==8'b00110011) begin // ASCII for "3"
      d=8'b00000011;
      d_hex=7'b0110000; // 7-segment display "3"
    end else if (distance==8'b00110100) begin // ASCII for "4"
      d=8'b00000100;
      d_hex=7'b0011001; // 7-segment display "4"
    end else if (distance==8'b00110101) begin // ASCII for "5"
      d=8'b00000101;
      d_hex=7'b0010010; // 7-segment display "5"
    end else if (distance==8'b00110110) begin // ASCII for "6"
      d=8'b00000110;
      d_hex=7'b0000010; // 7-segment display "6"
    end else if (distance==8'b00110111) begin // ASCII for "7"
      d=8'b00000111;
      d_hex=7'b1011000; // 7-segment display "7"
    end else if (distance==8'b00111000) begin // ASCII for "8"
      d=8'b00001000;
      d_hex=7'b0000000; // 7-segment display "8"
    end else if (distance==8'b00111001) begin // ASCII for "9"
      d=8'b00001001;
      d_hex=7'b0010000; // 7-segment display "9"
                end else begin
      if (homesw) begin
        d=8'b00000000;
        d_hex=7'b1000000;
      end else begin
        d=8'b00101000;
      end
    end
  end
end

endmodule


I am attempting to find a way for this to accept float/double values 
(2.2) and return the corresponding value.  Does anyone know of a quick 
way to do this?

Author: Dirk (Guest)
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At least for fixed point there is a library from IEEE named
fixed_pkg.

Until now I did not hear of something similar for floating point. 
Although I must say, that I didn't look for it because fixed point is 
enough for me until now.

I just saw that you dont write in VHDL, i asume it is verilog - I dont 
know if this libs work for verilog as well - sorry.

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