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Forum: FPGA, VHDL & Verilog VHDL beginner - signal conflict resolution


Author: Alexander Finch (Company: SSBV UK) (alexandicity)
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Hello all!

I'm new to VHDL and am looking to learn it as fast as possible. I've 
been reading all I can on the topic and think I have a fairly good grasp 
of what's going on. However, something bothers me about the 
simultaneousness of evaluation.

Take, for example, two processes. The first process assigns a binary '1' 
to a signal. Another process assigns '0' to the same signal. Given that 
both processes are converted to hardware which do not execute 
sequentially, both processes will simultaneously be trying to pull the 
signal in a conflicting manner. What happens in this situation? Have I 
misunderstood something that prevents this situation from occurring in 
the first place?

Thank you!
   Alexandicity

Author: Lothar Miller (lkmiller) (Moderator)
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> What happens in this situation?
Where?
In simulation: you will get a collision on this signal. When the 
assigned value is different it depends on the signals type how the 
simulator copes up with this problem. For std_logic a resolution table 
exists. With that the colliding signals will be resolved (and result 
usually in a 'X').

In hardware: you will not get synthesized such a description.
(Because todays fpgas don't have "wires" to which more than 1 output can 
be connected to...)

Author: Alexander Finch (Company: SSBV UK) (alexandicity)
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Ah, so this would be an invalid description that would cause errors, be 
they handled errors (as with your std_logic example), simulation errors 
(other binary types) or synthesis errors?

Author: Lothar Miller (lkmiller) (Moderator)
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You can and will get all three of them.
And maybe even if the simulation does not report an error (because your 
stimuli always drives the same value from both outsputs to the signal), 
the syntheses will not be able to resolve it...

Author: Alexander Finch (Company: SSBV UK) (alexandicity)
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Understood. Thanks for your clear and succinct response!

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