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Forum: FPGA, VHDL & Verilog Implementation error


Author: panner selvam (Company: sets) (panner224)
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I m simulated my code successfully and also generated the bit file.. 
while implemented in fpga v4 i m not getting the simulated output..

Author: user (Guest)
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aha, my crystal ball is out of order

Author: Lothar Miller (lkmiller) (Moderator)
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> while implemented in fpga v4 i m not getting the simulated output..
And what do you get instead? What errors/warnings do you get during the 
implementation? What is your actual question?

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