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Forum: FPGA, VHDL & Verilog arrary comparsion in VHDL


Author: Raghavendra B. (raghavendra_b98)
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Hi all

How to compare array in VHDL?

Thanks in advance

Author: Lothar Miller (lkmiller) (Moderator)
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> How to compare array in VHDL?
Usually you will have to compare each element of the array. But thats 
not a demanding task: just use a bunch of for-loops. But be aware: thats 
only good if you just want to simulate your design.

If your design is for the "real world" then maybe your array is stored 
in a RAM, and therefore you CANNOT access ALL of the elements IN 
PARALLEL. So you will have to pick one element out of the RAM after the 
other and compare the array on a step-by-step strategy...

> How to compare array in VHDL?
What size?

Author: Raghavendra B. (raghavendra_b98)
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Thanks lkmiller.

array size is one dimension.

actually doing declaring two arry. a and b is one array element and c 
and d another array element then perform below operation.
a * d
b * c

please guide me how to do.

Author: Lothar Miller (lkmiller) (Moderator)
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> please guide me how to do.
How would you do it with a programming language like BASIC or C?

What is your solution for?
Just for simulation or is it to be implemented on a FPGA?

> array size is one dimension.
Did you know: in VHDL already a vector is a one dimensional array?
Just have a look for the definition of std_logic_vector...

Author: Raghavendra B. (raghavendra_b98)
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Thanks you...just for simulation purpose only.

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