EmbDev.net

Forum: FPGA, VHDL & Verilog arrary comparsion in VHDL

Author: Raghavendra B. (raghavendra_b98)
Posted on:

Hi all

How to compare array in VHDL?

Thanks in advance
Author: Lothar Miller (lkmiller)
Posted on:

> How to compare array in VHDL?
Usually you will have to compare each element of the array. But thats
not a demanding task: just use a bunch of for-loops. But be aware: thats
only good if you just want to simulate your design.

If your design is for the "real world" then maybe your array is stored
in a RAM, and therefore you CANNOT access ALL of the elements IN
PARALLEL. So you will have to pick one element out of the RAM after the
other and compare the array on a step-by-step strategy...

> How to compare array in VHDL?
What size?
Author: Raghavendra B. (raghavendra_b98)
Posted on:

Thanks lkmiller.

array size is one dimension.

actually doing declaring two arry. a and b is one array element and c
and d another array element then perform below operation.
a * d
b * c

please guide me how to do.
Author: Lothar Miller (lkmiller)
Posted on:

> please guide me how to do.
How would you do it with a programming language like BASIC or C?

What is your solution for?
Just for simulation or is it to be implemented on a FPGA?

> array size is one dimension.
Did you know: in VHDL already a vector is a one dimensional array?
Just have a look for the definition of std_logic_vector...
Author: Raghavendra B. (raghavendra_b98)
Posted on:

Thanks you...just for simulation purpose only.

Reply

Entering an e-mail address is optional. If you want to receive reply notifications by e-mail, please log in.

Rules — please read before posting

  • Post long source code as attachment, not in the text
  • Posting advertisements is forbidden.

Formatting options

  • [c]C code[/c]
  • [avrasm]AVR assembler code[/avrasm]
  • [vhdl]VHDL code[/vhdl]
  • [code]code in other languages, ASCII drawings[/code]
  • [math]formula (LaTeX syntax)[/math]






webmaster@embdev.netContactAdvertising on EmbDev.net