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Forum: FPGA, VHDL & Verilog Counter problem - input not loading


Author: David O'Callaghan (mucker2b)
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Hi - first post here,

I am trying to describe a counter which accepts an address and 
increments by 1 each cycle. The problem is that the counter always 
starts at 0 even when reset is '0'. I have attached the code below. Can 
anybody see where I am going wrong? I thought that by assigning the 
value 'a' to 'temp_address' in the process that it would work as 
expected.
Any feedback welcome - thanks.

entity c1_new_address is
generic (n: integer := 14);
port (a: in std_logic_vector((n-1) downto 0);
    clk, reset: in std_logic;
    w: out std_logic_vector((n-1) downto 0));
end c1_new_address;

architecture Behavioral of c1_new_address is
signal temp_address: std_logic_vector((n-1) downto 0);
begin
  process(clk, reset)
  begin
    if reset = '1' then
    temp_address <= (others => '0');
    elsif rising_edge(clk) then
    temp_address <= a;
    temp_address <= conv_std_logic_vector((conv_integer(temp_address) + 
1), 14);
    end if;
  w <= temp_address;
  end process;
end Behavioral;

Author: PittyJ (Guest)
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There are two 'assignments' to temp_address:

 temp_address <= a;

 temp_address <= conv_std_logic_vector((conv_integer(temp_address) +
1), 14);


Which one should get calculated. As far as I know, the 'compiler' takes 
the last one and ignores all previous. Meaning the you will always get

 temp_address <= conv_std_logic_vector((conv_integer(temp_address) +
1), 14);

and
 temp_address <= a;
is discarded.

Author: David O'Callaghan (mucker2b)
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I thought that as a process runs statements sequentially that both 
assignments should get run in the order that they are in => on the 
rising edge, temp is assigned the ip value and it is incremented on the 
next statement.

I also tried assigning the value 'a' to temp_address outside the process 
so that the same value doesn't get assigned to temp_address during each 
run of the process with the ip address still not being assigned to 
temp_address.

Author: mifi (Guest)
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Hello David,

have you try this way:

temp_address <= conv_std_logic_vector((conv_integer(a) + 1), 14);

In this case there is only one statement.

Regards,
mifi

Author: Lothar Miller (lkmiller) (Moderator)
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> I thought that as a process runs statements sequentially that both
> assignments should get run in the order that they are in
The assignments do not run, and they are not executed. You are thinking 
in sequential software (like Basic or C). In real hardware all of your 
statements are executed at the exactly same time (at the moment the 
clock signal rises).

Having fixed that, you must have a look for the behaviour of signals in 
a VHDL process: they don't change their values until the end of the 
process. And then the last assignment "wins" and the signal gets its new 
value.

Here X never ever will have another value than 7, because thats the 
last assignment to this signal:
  process (A) begin
     X <= 1;
     X <= A+3;
     X <= 7;
  end process;

Here X never will increment, but just store the value of A:
  process (clk) begin
     if rising_edge(clk) then
       X <= 7;
       X <= X+1;
       X <= A;
     end if;
  end process;

And here X will simply count up:
  process (clk) begin
     if rising_edge(clk) then
       X <= 7;
       X <= X+1;
     end if;
  end process;

Author: David O'Callaghan (mucker2b)
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@ mifi - I used your method and it worked a treat.
@ Lothar - That was a simple and effective way of explaining the 
assignment operation in a process.
Thank you gentlemen.

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