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Forum: FPGA, VHDL & Verilog Ethernet controller


Author: blade blade (Company: sewrew) (blade_2011)
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Hello , i want to send data to my ethernet controller on my
FPGA(cyclone) board of Altera.
What algorithm of sending data via this interface ?? What first steps i
need to do in order to accomplish this mission. Maybe someone can advise
me some book that can help me in this project.
Thanks.

Author: Fetz (Guest)
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No problem at all ... Of course there is just one single model of FPGA 
board on the whole world, so it shouldn't be a problem to help you ;-)

Author: blade (Guest)
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Hi Fetz , ia want to specify my problem , I need information of how to 
do configuration of my ethernet controller on my FPGA board. Hence, how 
i say to controller that i want to work in full duplex ?? speed ? How 
configure the Ethernet PHY registers to operate in 10/100/Gigabit Mode 
??

Author: Fetz (Guest)
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Sorry, if you don't get it ... There is more than one board out there 
and there is more than one ethernet-controller out there and so on and 
so on ...

Nobody will be able to help you if you don't tell us your exact 
model of your FPGA board ...

Author: blade blade (Company: sewrew) (blade_2011)
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Cyclone III FPGA development board(Cyclone III EP3C120F780 FPGA)

Author: PittyJ (Guest)
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More important than the FPGA-type is the used PHY.

I use a marvel 88E1111. For this chip the correct reset sequence is 
important. Second this chips needs a GTX-Clock, which has a phase of 90 
degrees. This can be done by a PLL.

Altera offers an Ethernet IP-core (Triple Speed Ethernet TSE), which 
supports also this Phy. I use this core, a self written reset-logic, and 
can receive data from ethernet.

The PHY itself is controlled over the MDIO interface. The TSE maps the 
phy-registers, that you dont have to access MDIO by yourself.

Author: blade (Guest)
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Hi PittyJ , I also use the same chip , what is it reset-logic ? What the 
purpose of this logic ?  In general , do you know maybe some good book 
about configuration ethernet controller on FPGA ??

Author: PittyJ (Guest)
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There is no good book.

I gathered all information out of several buletin boards (like this 
here).
Marvell has a Technical Data Sheet, but you get it only under a NDA. So 
I had to work without it.

The reset logic is a simple state machine:
Wait 10 msec before apply the reset signal.
Do the reset signal for at least 10 msec.
Wait a longer time, (I used 3 seconds) before accessing the chip.

Next step would set up the MDIO registers.
This can be done over setting values in the TSE register section.

In the Altera TSE-Documentation the registers are described (section 5, 
Mac configuration register space)

Author: blade (Guest)
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PittyJ, thank you for information !!

Author: René D. (Company: www.dossmatik.de) (dose)
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First you have to know what Interface is wired.
Marvell Phy can use different types


GMII, MII, or RMII or ...

Often you can found some information in applocation notes.

Author: blade (Guest)
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Hi René D. , interface that wired it RGMII Interface.

Author: René D. (Company: www.dossmatik.de) (dose)
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blade wrote:
> Hi René D. , interface that wired it RGMII Interface.

I have only the other direction in VHDL. Send from FPGA with GMII.


The phy running normaly without any initialisation.

Have you some LEDs direcly on the phy?
Connected 100M,10M 1G packet reseive, packet send

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