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Forum: FPGA, VHDL & Verilog Error when ran make file


Author: (unknown) (Guest)
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Hi.I written VHDL code once i ran my make file in GHDL simulator it 
gives below error.


ghdl1: fatal error: can’t open work/e~my file name.s for writing: No 
such file or directory

Thanks in advance

Regards
Raghavendra

Author: Grey (Guest)
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the error is already mentioned: the file is missing or ghdl has no write 
access in this directory. do u checked this?

Author: (unknown) (Guest)
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Thanks for your replay.I checked and corrected my work directory.

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