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Forum: FPGA, VHDL & Verilog help for Signal_quiet attribute


Author: sreeram sam (sresam89)
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i used a code
x:=ORFLAG'QUIET(400 ns)

xilinx shows an error
"The predefined attribute QUIET is unsupported"

can anyone help.am i not using any special pacakages for this?

Author: Lothar Miller (lkmiller) (Moderator)
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Read the "XST Users Guide".
You will find out, that the simulator can simulate much more than the 
synthesizer can transfer to hardware. And you will also see: most of the 
VHDL attributes are not synthesizeable.

Author: sreeram sam (sresam89)
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Lothar Miller wrote:
> Read the "XST Users Guide".
> You will find out, that the simulator can simulate much more than the
> synthesizer can transfer to hardware. And you will also see: most of the
> VHDL attributes are not synthesizeable.

thanks lothar.

sir it was your piece of code suggestion i tried for the stuck at fault 
topic
http://embdev.net/topic/235605

can you please suggest any other alternative..

Author: Lothar Miller (lkmiller) (Moderator)
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> sir it was your piece of code suggestion i tried
Yes, but there you did write:
>>>  the code is for simulation only
And in simulation this will work.
But not (and never) for synthesis on real hardware!

> can you please suggest any other alternative..
>>> can anyone please give me a piece of vhdl code for stuck at faults
>>> stuck-at-0 and stuck-at-1 for any sequential and/or combination
>>> circuits, just need it to start from the scratch.
Pls clarify what you want to do with this code? Waht do you need it 
for?

Author: sreeram sam (sresam89)
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> Pls clarify what you want to do with this code? Waht do you need it
> for?

sorry sir,
i noticed that u said it was only for simulation.

i need the code to to compiled using xilinx and see the simulation using 
modelsim .

Author: Lothar Miller (lkmiller) (Moderator)
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> i need the code to to compiled using xilinx and see the simulation using
> modelsim .
Thats no answer to my question!
I just wanted to knwo: WHAT do you want to do? WHAT is your primary 
task? WHERE does the signal come from? WHERE does the result go to?


> can you please suggest any other alternative..
In a real synchronous hardware design every time is realized by a 
counter.
So if you want to check a signal for a stuck-at-1 for a certain time (in 
your case obviously 400ns) and you have a clock (lets say 50MHz =20ns), 
you can do it that way:
   signal cnthigh : integer := 0;        -- count the duration of the high phase 
   signal stuckatone : std_logic := '0'; -- flag the stuck failure
:
:
   process begin
      wait until rising_edge(clk50mhz);
      if (cnthigh > 400/20) then -- end of time reached?
         stuckatone<='1';        -- we have a stucked signal
      end if;
      if (input='1') then        -- if the input is 1
         cnthigh <= cnthigh+1;   -- count up
      else                       -- if the input is 0
         cnthigh <= 0;           -- reset the counter
      end if; 
   end process;

Author: sreeram sam (sresam89)
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thanks miller.

Lothar Miller wrote:
>> i need the code to to compiled using xilinx and see the simulation using
>> modelsim .
> Thats no answer to my question!
> I just wanted to knwo: WHAT do you want to do? WHAT is your primary
> task? WHERE does the signal come from? WHERE does the result go to?

my primary task will be to find the faults at basic gates. for the gates 
i will use separate process or testbench for each one of them.

the signals for the gates comes from a Test pattern generator. no user 
given inputs are necessary if not considering the clock that has to be 
provided in the modelsim, no FPGA implementation is to be done.the 
output of gates are to used just for fault recognition, and are of no 
use further.

this is my task to be done

Author: Lattice User (Guest)
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> no FPGA implementation is to be done

This begs the question:
Why do you need then to compile with the Xilinx Synthesiser?

Author: Lothar Miller (lkmiller) (Moderator)
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> my primary task will be to find the faults at basic gates.
In REAL HARDWARE or only for with a SIMULATION?
I didn't figure out this up to now...   :-/

> the signals for the gates comes from a Test pattern generator.
= hardware?
> no user
> given inputs are necessary if not considering the clock that has to be
> provided in the modelsim,
= simulation
> no FPGA implementation is to be done.
= simulation or ASIC
> the output of gates
= hardware?
> are to used just for fault recognition, and are of no use further.

Author: sreeram sam (sresam89)
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Lattice User wrote:
>> no FPGA implementation is to be done
>
> This begs the question:
> Why do you need then to compile with the Xilinx Synthesiser?

i personally use xilinx to compose n compile the codes in vhdl.
any other suggestions?

Author: sreeram sam (sresam89)
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Lothar Miller wrote:
>> my primary task will be to find the faults at basic gates.
> In REAL HARDWARE or only for with a SIMULATION?
> I didn't figure out this up to now...   :-/
sir i dont implement these codes in FPGA kits.I compile them under 
xilinx and just simulate them in modelsim.
>
>> the signals for the gates comes from a Test pattern generator.
> = hardware?
no the TPG is also software written

>> no user given inputs are necessary if not considering the clock that has to be 
provided in the modelsim,
> = simulation

yes am given only clock cycles for Test pattern generation that too in 
simulation in modelsim.

>> no FPGA implementation is to be done.
> = simulation or ASIC

simulation only

>> the output of gates
> = hardware?

not hardware just to see the simulated output in modelsim(output need to 
be something which tell whether fault is present or not, could probably 
be a report statement as u had given in the first post.)

>> are to used just for fault recognition, and are of no use further.
yes am not going to use the output of the gates any further.


thanks for your precious time millar.
awaiting your reply

Author: Lattice User (Guest)
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What you want to do can be done with the FPGA design flow, but you need 
clearly understand what the difference between testbench and DUT (device 
undet test) is. Testing on stuck signals, testpattern generator etc 
belongs in the testbench. If done correctly the synthesiser will never 
see it (in your case you don't even need to compile the synthesiser).

I think you are better served with a stand alone simulator. For example 
Modelsim (i have no idea if the Xilinx version can be used standalone), 
Aldec HDL or even GHDL.

Author: Lothar Miller (lkmiller) (Moderator)
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> I compile them under xilinx
Why?
> and just simulate them in modelsim.
All of the work only must be simulated, and thats the only thing that 
makes sense. FORGET the synthesis with XST. Why (at all) do you setup 
the project in ISE? Do your work COMPLETELY in ModelSim. And never ever 
check the design with a synthesizer...

Then the asttribute 'QUIET will work fine, and also the other ones....

Author: sreeram sam (sresam89)
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Lothar Miller wrote:
>> I compile them under xilinx
> Why?
>> and just simulate them in modelsim.
> All of the work only must be simulated, and thats the only thing that
> makes sense. FORGET the synthesis with XST. Why (at all) do you setup
> the project in ISE? Do your work COMPLETELY in ModelSim. And never ever
> check the design with a synthesizer...
>
> Then the asttribute 'QUIET will work fine, and also the other ones....

will ask you if any more query after i try them all in modelsim.

thanks for your precious support.

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