Forum: FPGA, VHDL & Verilog loading hex data into RAM

Author: pakhi new (manideepa) Flattr this
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Hi all,
I want to read data from a file in vhdl.In verilog readmemh is used, but 
please help me how to do that in vhdl.

Author: PittyJ (Guest)
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Look into the book "The designers guide to VHDL" from Peter Ashenden.
The complete chapter 16 describes the file IO.

Author: Lothar Miller (lkmiller) (Moderator)
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Search on Google for "hread vhdl".
Also try this with babelfish or google translator: 
Beitrag "Problem Textio"

And, after all is said by PittyJ, there is one thing to remark:

@ Manideepa Mukherjee
why do you NEVER give a backlink to previous thrads with your own 
similar questions? Why do you open a new thread Same as already 
mentioned in the thread http://embdev.net/topic/240778#2447717

Author: pakhi new (manideepa) Flattr this
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Attached files:

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I tried loading data using the attached file it is simulator is giving 
the following warning:

Simulation object /RLD/RAM was not traceable in the design for the 
following reason:
The number of elements in the requested object is 200008, which exceeds 
the maximum traceable size of 65536 elements.  The maximum can be 
changed with the "isim set maxtraceablesize" Tcl command.
Simulator is doing circuit initialization process.
Finished circuit initialization process.

please help

Author: srinivasa c. (srinivasa_c)
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dear sir,

we are working on data compression and we have to implement it using 
serial and parallel methods, please help us for the following problem v 
r facing while implementing-

1.how to clear" numeric_bit denoted by prefix ieee must exist in must 
exist in the library" in altera max plus ii????

2. how to write LOOK UP TABLE program for huffman decoder??

3. is there any way to implement look up table in GRAPHIC EDITIOR MODE 
in altera???

4. should we send huffman tree for decoding along with look up table for 

kindly, reply us soon.........
thank you.


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