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Forum: FPGA, VHDL & Verilog Failure: (vsim-3807) Types do not match between component and entity for port "out1".


von nd d. (Company: KPTM) (dee)


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Hi, i got error in model-sim altera,Failure: (vsim-3807) Types do not 
match between component and entity for port "out1". I got also failure 
for port out2 and so on.

When i check component in haar_tb.vhd : testbench file is same with 
entity in haar.vhd. Can I know what the solution for this problem.i got 
the error message when i click on EDA Gate Level simulation. please help 
me.

this haar.vhd:

1
LIBRARY ieee;
2
USE ieee.ALL;
3
ENTITY haar IS
4
PORT (
5
clock : IN bit;
6
-- Inputs
7
in1 : IN integer RANGE -127 TO 127;
8
in2 : IN integer RANGE -127 TO 127;
9
in3 : IN integer RANGE -127 TO 127;
10
in4 : IN integer RANGE -127 TO 127;
11
in5 : IN integer RANGE -127 TO 127;
12
in6 : IN integer RANGE -127 TO 127;
13
in7 : IN integer RANGE -127 TO 127;
14
in8 : IN integer RANGE -127 TO 127;
15
--Outputs
16
out1 : out integer RANGE -127 TO 127;
17
out2 : OUT integer RANGE -127 TO 127;
18
out3 : OUT integer RANGE -127 TO 127;
19
out4 : OUT integer RANGE -127 TO 127;
20
out5 : OUT integer RANGE -127 TO 127;
21
out6 : OUT integer RANGE -127 TO 127;
22
out7 : OUT integer RANGE -127 TO 127;
23
out8 : OUT integer RANGE -127 TO 127);
24
END haar;
25
ARCHITECTURE haar OF haar IS
26
27
COMPONENT reg
28
29
PORT (
30
input : IN integer RANGE -127 TO 127;
31
clock : IN bit;
32
output : Out integer RANGE -127 TO 127
33
);
34
END COMPONENT;
35
COMPONENT adddiv
36
PORT (
37
a : IN integer RANGE -127 TO 127;
38
b : in integer RANGE -127 TO 127;
39
clock : IN bit;
40
c : out integer RANGE -127 TO 127
41
);
42
END COMPONENT;
43
COMPONENT difference
44
PORT (
45
a : IN integer RANGE -127 TO 127;
46
b : in integer RANGE -127 TO 127;
47
clock : IN bit;
48
c : out integer RANGE -127 TO 127
49
);
50
END COMPONENT;
51
SIGNAL out_r1, out_r2, out_r3, out_r4, out_r5, out_r6, out_r7,
52
out_r8 : integer RANGE -127 TO 127;
53
SIGNAL out_a1, out_a2, out_a3, out_a4, out_a5, out_a6, out_a7,
54
out_a8 : integer RANGE -127 TO 127;
55
SIGNAL out_s1, out_s2, out_s3, out_s4, out_s5, out_s6, out_s7,
56
out_s8 : integer RANGE -127 TO 127;
57
SIGNAL clk : bit;
58
BEGIN
59
-- Input to Register here
60
r1: reg
61
PORT MAP ( in1, clock, out_r1 );
62
r2: reg
63
64
PORT MAP ( in2, clock, out_r2 );
65
r3: reg
66
PORT MAP ( in3, clock, out_r3 );
67
r4: reg
68
PORT MAP ( in4, clock, out_r4 );
69
r5: reg
70
PORT MAP ( in5, clock, out_r5 );
71
r6: reg
72
PORT MAP ( in6, clock, out_r6 );
73
r7: reg
74
PORT MAP ( in7, clock, out_r7 );
75
r8: reg
76
PORT MAP ( in8, clock, out_r8 );
77
-- Input to Add_Divide and Difference for stage 1
78
a1: adddiv
79
PORT MAP ( out_r1, out_r2, clock, out_a1 );
80
a2: adddiv
81
PORT MAP ( out_r3, out_r4, clock, out_a2 );
82
a3: adddiv
83
PORT MAP ( out_r5, out_r6, clock, out_a3 );
84
a4: adddiv
85
PORT MAP ( out_r7, out_r8, clock, out_a4 );
86
s1: difference
87
PORT MAP ( out_r1, out_r2, clock, out_s1 );
88
s2: difference
89
PORT MAP ( out_r3, out_r4, clock, out_s2 );
90
s3: difference
91
PORT MAP ( out_r5, out_r6, clock, out_s3 );
92
s4: difference
93
PORT MAP ( out_r7, out_r8, clock, out_s4 );
94
-- Input to AddDiv and Difference for stage 2
95
a5: adddiv
96
PORT MAP ( out_a1, out_a2, clock, out_a5 );
97
a6: adddiv
98
PORT MAP ( out_a3, out_a4, clock, out_a6 );
99
s5: difference
100
PORT MAP ( out_a1, out_a2, clock, out_s5 );
101
s6: difference
102
PORT MAP ( out_a3, out_a4, clock, out_s6 );
103
a7: adddiv
104
PORT MAP ( out_s1, out_s2, clock, out_a7 );
105
a8: adddiv
106
PORT MAP ( out_s3, out_s4, clock, out_a8 );
107
s7: difference
108
PORT MAP ( out_s1, out_s2, clock, out_s7 );
109
s8: difference
110
PORT MAP ( out_s3, out_s4, clock, out_s8 );
111
-- Input to AddDiv and Difference for stage 3
112
a9: adddiv
113
PORT MAP ( out_a5, out_a6, clock, out1 );
114
s9: difference
115
PORT MAP ( out_a5, out_a6, clock, out2 );
116
a10: adddiv
117
PORT MAP ( out_s5, out_s6, clock, out3 );
118
s10: difference
119
PORT MAP ( out_s5, out_s6, clock, out4 );
120
a11: adddiv
121
PORT MAP ( out_a7, out_a8, clock, out5 );
122
s11: difference
123
PORT MAP ( out_a7, out_a8, clock, out6 );
124
a12: adddiv
125
PORT MAP ( out_s7, out_s8, clock, out7 );
126
s12: difference
127
PORT MAP ( out_s7, out_s8, clock, out8 );
128
END haar;



this vhdl testbench haar_tb.vhd



-- Vhdl Test Bench template for design  :  haar
--
-- Simulation tool : ModelSim-Altera (VHDL)
--
1
LIBRARY ieee;                                               
2
USE ieee.all;
3
use IEEE.Std_logic_1164.all;
4
use IEEE.Numeric_Std.all;
5
6
7
8
ENTITY haar_tb IS
9
END haar_tb;
10
ARCHITECTURE haar_arch OF haar_tb IS
11
-- constants   
12
component haar
13
PORT (
14
clock : IN bit;
15
-- Inputs
16
in1 : IN integer RANGE -127 TO 127;
17
in2 : IN integer RANGE -127 TO 127;
18
in3 : IN integer RANGE -127 TO 127;
19
in4 : IN integer RANGE -127 TO 127;
20
in5 : IN integer RANGE -127 TO 127;
21
in6 : IN integer RANGE -127 TO 127;
22
in7 : IN integer RANGE -127 TO 127;
23
in8 : IN integer RANGE -127 TO 127;
24
--Outputs
25
out1 : out integer RANGE -127 TO 127;
26
out2 : OUT integer RANGE -127 TO 127;
27
out3 : OUT integer RANGE -127 TO 127;
28
out4 : OUT integer RANGE -127 TO 127;
29
out5 : OUT integer RANGE -127 TO 127;
30
out6 : OUT integer RANGE -127 TO 127;
31
out7 : OUT integer RANGE -127 TO 127;
32
out8 : OUT integer RANGE -127 TO 127);
33
 end component;
34
35
36
37
38
39
                                              
40
-- signals                                 
41
42
  signal clock: bit;
43
  signal in1: integer RANGE -127 TO 127;
44
  signal in2: integer RANGE -127 TO 127;
45
  signal in3: integer RANGE -127 TO 127;
46
  signal in4: integer RANGE -127 TO 127;
47
  signal in5: integer RANGE -127 TO 127;
48
  signal in6: integer RANGE -127 TO 127;
49
  signal in7: integer RANGE -127 TO 127;
50
  signal in8: integer RANGE -127 TO 127;
51
  signal out1: integer RANGE -127 TO 127;
52
  signal out2: integer RANGE -127 TO 127;
53
  signal out3: integer RANGE -127 TO 127;
54
  signal out4: integer RANGE -127 TO 127;
55
  signal out5: integer RANGE -127 TO 127;
56
  signal out6: integer RANGE -127 TO 127;
57
  signal out7: integer RANGE -127 TO 127;
58
  signal out8: integer RANGE -127 TO 127;
59
60
61
62
63
BEGIN
64
  uut : haar
65
  PORT MAP (
66
-- list connections between master ports and signals
67
  clock => clock,
68
  in1 => in1,
69
  in2 => in2,
70
  in3 => in3,
71
  in4 => in4,
72
  in5 => in5,
73
  in6 => in6,
74
  in7 => in7,
75
  in8 => in8,
76
  out1 => out1,
77
  out2 => out2,
78
  out3 => out3,
79
  out4 => out4,
80
  out5 => out5,
81
  out6 => out6,
82
  out7 => out7,
83
  out8 => out8
84
  );
85
init : PROCESS                                               
86
-- variable declarations                                     
87
BEGIN                                                        
88
        -- code that executes only once     
89
90
clock<='0';
91
wAIT for 10 ns;
92
clock<='1'; 
93
wait for 10 ns;                                                    
94
END PROCESS init;                                           
95
always : PROCESS                                              
96
-- optional sensitivity list                                  
97
-- (        )                                                 
98
-- variable declarations                                      
99
BEGIN                                                         
100
        -- code executes for every event on sensitivity list  
101
in1<= 18;
102
in2<= 5;
103
in3<= 1;
104
in4<= 9;
105
in5<= 13;
106
in6<= 6;
107
in7<= 2;
108
in8<= 3;
109
  
110
WAIT for 50 ns; 
111
  
112
---------------------Second Test------------------
113
in1 <= 9;
114
in2 <= 2;
115
in3 <= 12;
116
in4 <= 5;
117
in5 <= 10;
118
in6 <= 60;
119
in7 <= 23;
120
in8 <= 13;
121
wait for 50ns;
122
---------------------Third Test--------------------
123
in1 <= 18;
124
in2 <= 52;
125
in3 <= 11;
126
in4 <= 1;
127
in5 <= 8;
128
in6 <= 61;
129
in7 <= 28;
130
in8 <= 77;
131
wait for 50ns;
132
133
wait;
134
END PROCESS always;                                          
135
END haar_arch;
136
137
138
configuration CFG_TB of haar_TB is 
139
for haar_arch 
140
end for; 
141
end CFG_TB;


Thank you.

von Lothar M. (Company: Titel) (lkmiller) (Moderator)


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> Can I know what the solution for this problem
Try it this way: define a package with your constrained integer as a new 
(sub-)type. And then pass this "costumized" type on the port.

With a "customized" type you can also take advantage to write the 
complete code shorter and more generic.

von nd d. (Company: KPTM) (dee)


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I create  1 file named haar_gate.vhd for gate implementation

do you mean like this code:
1
LIBRARY ieee;
2
USE ieee.ALL;
3
use ieee.std_logic_1164.all;
4
use ieee.std_logic_arith.all;
5
6
package data_types is
7
subtype byte is integer range -127 to 127;
8
end data_types;
9
10
11
LIBRARY ieee;
12
use ieee.std_logic_1164.all;
13
use ieee.std_logic_arith.all;
14
15
ENTITY haar_gate is
16
17
generic (byte : integer:= 8);
18
19
PORT (
20
clock : IN bit;
21
in1 ,in2,in3,in4,in5,in6,in7,in8: IN integer;
22
out1 ,out2,out3,out4,out5,out6,out7,out8: out integer);
23
END haar_gate;
24
25
ARCHITECTURE haar OF haar_gate IS
26
--as before
27
END haar;


But i got the same error.....
sorry, i'm beginner in vhdl code

Thanks for response

von Lothar M. (Company: Titel) (lkmiller) (Moderator)


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Ok one step back. Try this simple design:
1
LIBRARY ieee;
2
USE ieee.ALL; -- seems to be a nice idea, 
3
              -- but beware of double type definitions!
4
5
entity intport is
6
    Port ( clk : in  bit;
7
           di  : in  integer RANGE -127 TO 127;
8
           do  : out integer RANGE -127 TO 127
9
          );
10
end intport;
11
12
architecture Behavioral of intport is
13
14
begin
15
   do <= di when (clk='1' and clk'event);
16
end Behavioral;

With this simple testbench:
1
LIBRARY ieee;
2
USE ieee.std_logic_1164.ALL;
3
USE ieee.numeric_std.ALL;
4
 
5
ENTITY tb_intport IS
6
END tb_intport;
7
 
8
ARCHITECTURE behavior OF tb_intport IS 
9
    COMPONENT intport
10
    PORT(  clk : IN  bit;
11
           di  : in  integer RANGE -127 TO 127;
12
           do  : out integer RANGE -127 TO 127);
13
    END COMPONENT;
14
15
   signal clk : bit := '0';
16
   signal di : integer range  -127 TO 127 := 0;
17
   signal do : integer range  -127 TO 127;
18
   signal s : signed(7 downto 0) := (others=>'0');
19
20
BEGIN
21
   uut: intport PORT MAP (
22
          clk => clk,
23
          di => di,
24
          do => do
25
        );
26
27
   clk <= not clk after 5 ns;
28
   s <= s+1 after 10 ns;
29
   di <= to_integer(s);
30
END;

What do you get as result? Is it working?

von nd d. (Company: KPTM) (dee)


Attached files:

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yes, it is working.

when i click on EDA RTL simulation -  successful
the output as inport.jpg:
example
if di=0
when clk='1' and clk'event
do=0

di is input from 0 to 127
do is output (-127 when clk ='1' and clk'event ,the output is 0 to 127)
s =>s+1 after 10 ns (the binary of input).


when i click on EDA Gate level Simulation--i got error as the following:


# Reading C:/altera/11.1/modelsim_ase/tcl/vsim/pref.tcl
# do intport_run_msim_gate_vhdl.do
# if {[file exists gate_work]} {
#   vdel -lib gate_work -all
# }
# vlib gate_work
# vmap work gate_work
# Copying C:\altera\11.1\modelsim_ase\win32aloem/../modelsim.ini to 
modelsim.ini
# Modifying modelsim.ini
# ** Warning: Copied 
C:\altera\11.1\modelsim_ase\win32aloem/../modelsim.ini to modelsim.ini.
#          Updated modelsim.ini.
#
# vcom -93 -work work {intport_2_1100mv_85c_slow.vho}
# Model Technology ModelSim ALTERA vcom 10.0c Compiler 2011.09 Sep 21 
2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package VITAL_Timing
# -- Loading package VITAL_Primitives
# -- Loading package dffeas_pack
# -- Loading package altera_primitives_components
# -- Loading package std_logic_arith
# -- Loading package stratixiii_atom_pack
# -- Loading package stratixiii_components
# -- Compiling entity intport
# -- Compiling architecture structure of intport
#
# vcom -93 -work work {C:/Users/Public/Documents/learn/tb_intport.vhd}
# Model Technology ModelSim ALTERA vcom 10.0c Compiler 2011.09 Sep 21 
2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Compiling entity tb_intport
# -- Compiling architecture behavior of tb_intport
#
# vsim -t 1ps +transport_int_delays +transport_path_delays -sdftyp 
/uut=intport_2_1100mv_85c_vhd_slow.sdo -L altera -L stratixiii -L 
gate_work -L work -voptargs="+acc" tb_intport
# vsim +transport_int_delays +transport_path_delays -L altera -L 
stratixiii -L gate_work -L work -voptargs=\"+acc\" -sdftyp 
/uut=intport_2_1100mv_85c_vhd_slow.sdo -t 1ps tb_intport
# Loading std.standard
# Loading std.textio(body)
# Loading ieee.std_logic_1164(body)
# Loading ieee.numeric_std(body)
# Loading work.tb_intport(behavior)
# SDF 10.0c Compiler 2011.09 Sep 21 2011
#
# Loading ieee.vital_timing(body)
# Loading ieee.vital_primitives(body)
# Loading altera.dffeas_pack
# Loading altera.altera_primitives_components
# Loading ieee.std_logic_arith(body)
# Loading stratixiii.stratixiii_atom_pack(body)
# Loading stratixiii.stratixiii_components
# Loading work.intport(structure)
# ** Failure: (vsim-3807) Types do not match between component and 
entity for port "clk".
#    Time: 0 ps  Iteration: 0  Instance: /tb_intport/uut File: 
intport_2_1100mv_85c_slow.vho Line: 40
# Loading stratixiii.stratixiii_io_ibuf(arch)
# Loading stratixiii.stratixiii_io_obuf(arch)
# Loading stratixiii.stratixiii_clkena(vital_clkena)
# Loading stratixiii.stratixiii_ena_reg(behave)
# Loading stratixiii.stratixiii_and2(altvital)
# Loading stratixiii.stratixiii_lcell_comb(vital_lcell_comb)
# Loading altera.dffeas(vital_dffeas)
# Fatal error at intport_2_1100mv_85c_slow.vho line 40
#  while elaborating region: /tb_intport/uut
# Fatal error in file C:/Users/Public/Documents/learn/tb_intport.vhd
#  while elaborating region: /tb_intport
# Loading instances from intport_2_1100mv_85c_vhd_slow.sdo
# Loading timing data from intport_2_1100mv_85c_vhd_slow.sdo
# Load interrupted
# Error loading design
# Error: Error loading design
#        Pausing macro execution
# MACRO ./intport_run_msim_gate_vhdl.do PAUSED at line 12

von Lothar M. (Company: Titel) (lkmiller) (Moderator)


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> RTL simulation -  successful
Fine.
> Gate level Simulation
Who needs this?


However:
Give it a second try with
  USE ieee.std_logic_1164.ALL;
instead of
  USE ieee.ALL;
and std_logic instead of bit...

von nd d. (Company: KPTM) (dee)


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Did you mean like this:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

entity intport is
    Port ( clk : in  bit;
           di  : in  integer RANGE -127 TO 127;
           do  : out integer RANGE -127 TO 127
          );
end intport;

architecture Behavioral of intport is

begin
   do <= di when (clk='1' and clk'event);
end Behavioral;


When Gate Level Simulation, i got same error:


# ** Failure: (vsim-3807) Types do not match between component and 
entity for port "do".
#    Time: 0 ps  Iteration: 0  Instance: /tb_intport/uut File: 
intport_2_1100mv_85c_slow.vho Line: 38
# ** Failure: (vsim-3807) Types do not match between component and 
entity for port "clk".
#    Time: 0 ps  Iteration: 0  Instance: /tb_intport/uut File: 
intport_2_1100mv_85c_slow.vho Line: 39
# ** Failure: (vsim-3807) Types do not match between component and 
entity for port "di".
#    Time: 0 ps  Iteration: 0  Instance: /tb_intport/uut File: 
intport_2_1100mv_85c_slow.vho Line: 40


I got error in gate level simulation,is it effect when loading program 
into fpga?

von Lothar M. (Company: Titel) (lkmiller) (Moderator)


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> I got error in gate level simulation,
Who needs a gate level simulation?
> is it effect when loading program into fpga?
Look at the synthesizer messages.
If you can't see any errors there, your design will run fine.

Look at this simple piece of codee:
1
signal cnt : integer range 0 to 15;
2
:
3
:
4
cnt <= cnt + 1 when rising_edge(clk);
For hardware synthesis this will result in a 4 bit counter.
But the simulation will lead to major problems when cnt reaches 15.

von saba10 (Guest)


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hi ,
        i had the same problem.it was fine with the pre-synthesis 
simulation but i got the following error message when i tried a 
post-synthesis simulation ....

# ** Failure: (vsim-3807) Types do not match between component and 
entity for port "fs1".
#    Time: 0 ps  Iteration: 0  Instance: /tb_afsk/uut File: 
C:/Actelprj/afsk/synthesis/afsk.vhd Line: 12
# ** Failure: (vsim-3807) Types do not match between component and 
entity for port "data_in".
#    Time: 0 ps  Iteration: 0  Instance: /tb_afsk/uut File: 
C:/Actelprj/afsk/synthesis/afsk.vhd Line: 13
# Loading std.textio(body)
# Loading ieee.vital_timing(body)
# Loading ieee.vital_primitives(body)
# Loading proasic3.vtables
# Loading proasic3.or2(vital_act)
# Loading proasic3.xor2(vital_act)
# Loading proasic3.inbuf(vital_act)
# Loading proasic3.or2b(vital_act)
# Loading proasic3.or2a(vital_act)
# Loading proasic3.oa1b(vital_act)
# Loading proasic3.dfn1e0(vital_act)
# Loading proasic3.xnor2(vital_act)
# Loading proasic3.ax1a(vital_act)
# Loading proasic3.nor3a(vital_act)
# Loading proasic3.nor2b(vital_act)
# Loading proasic3.xa1(vital_act)
# Loading proasic3.ax1c(vital_act)
# Loading proasic3.ao1(vital_act)
# Loading proasic3.ao1c(vital_act)
# Loading proasic3.xnor3(vital_act)
# Loading proasic3.nor3c(vital_act)
# Loading proasic3.axo5(vital_act)
# Loading proasic3.dfn1e1c1(vital_act)
# Loading proasic3.axo1(vital_act)
# Loading proasic3.ax1b(vital_act)
# Loading proasic3.ao1b(vital_act)
# Loading proasic3.nor2a(vital_act)
# Loading proasic3.xa1a(vital_act)
# Loading proasic3.ax1(vital_act)
# Loading proasic3.aoi1b(vital_act)
# Loading proasic3.aoi1(vital_act)
# Loading proasic3.ax1e(vital_act)
# Loading proasic3.nor3(vital_act)
# Loading proasic3.xai1a(vital_act)
# Loading proasic3.ax1d(vital_act)
# Loading proasic3.oai1(vital_act)
# Loading proasic3.nor2(vital_act)
# Loading proasic3.oa1a(vital_act)
# Loading proasic3.oa1(vital_act)
# Loading proasic3.and2(vital_act)
# Loading proasic3.nor3b(vital_act)
# Loading proasic3.gnd(vital_act)
# Loading proasic3.outbuf(vital_act)
# Loading proasic3.vcc(vital_act)
# Loading proasic3.and3(vital_act)
# Loading proasic3.min3(vital_act)
# Loading proasic3.or3c(vital_act)
# Loading proasic3.axo2(vital_act)
# Loading proasic3.ao18(vital_act)
# Loading proasic3.mx2c(vital_act)
# Loading proasic3.mx2a(vital_act)
# Loading proasic3.xor3(vital_act)
# Loading proasic3.or3a(vital_act)
# Loading proasic3.clkbuf(vital_act)
# Loading proasic3.axoi1(vital_act)
# Loading proasic3.ao1d(vital_act)
# Loading proasic3.maj3(vital_act)
# Loading proasic3.mx2(vital_act)
# Loading proasic3.ao1a(vital_act)
# Loading proasic3.oa1c(vital_act)
# Loading proasic3.dfn1e0c1(vital_act)
# Fatal error at C:/Actelprj/afsk/synthesis/afsk.vhd line 13
#  while elaborating region: /tb_afsk/uut
# Fatal error in file C:/Actelprj/afsk/stimulus/tb_afsk.vhd
#  while elaborating region: /tb_afsk
# Error loading design
# Error: Error loading design
#        Pausing macro execution
# MACRO ./run.do PAUSED at line 15

i would be very thankful if you can help me with solution for this 
problem ??

von bko (Guest)


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your synthesis must have generated a VHDL-netlist. Try to find
this netlist - open it in an editor, then look
for the porttypes of your desin toplevel ...

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