i want hard ware decoder for this RlE encoder. plese help if any one has any idea about the hardware for the decoding of the encoded file. I need to decompress a .bit file compressed by this software,,,......
> to decompress a .bit file compressed by this software
So: how do you read this bit file?
Where is it located?
How can you access it?
Where does it go to?
Last but not least: what kind of hardware do you want?
If you say: there is a file on a hard drive. This I want to access with
"real" hardware, decode it, and store it back again.
Then I would say: this is a fairly demanding task, it will take at least
half a year full time...
Thanks for the reply! I want a VHDL code for the decompressor that will decompress the .bit file in the same way as it was compressed using this software. I need to calculate the critical path delay and the no. of cycle it is taking to decompress a file. for simulation i can read a file from the disk in vhdl right? if u have any idea about the code which will take data from a file and simulate it please help.....as early as possible.
> for simulation i can read a file from the disk in vhdl right? So you want to do it only for simulation? > if u have any idea about the code which will take data from a file > and simulate it please help.....as early as possible. You will need the fileio functions to read the ingoing data out of a file. Then you process it, and afterwards you write it back in a new file. So first step for you is to read in the data, second is to write it back again, and third is to modify it in between. For the first two tasks turn on Google for "vhdl fileio". When this works, you can focus on the decoding...
Manideepa Mukherjee wrote: > I need to calculate the critical path delay and the no. of > cycle it is taking to decompress a file. This values depends strongly on how the algorithm is implemented on the FPGA. But why don't you give some background information on what do you really want to do? From your question it seems you don't have clear ideas about what FPGAs are and how they are used.
Hi, I am trying to explain what i want to do. I want to make a decompressor in VHDL which will decompress configuration file(.bit) using the above algorithm. The software which I attach is compressing a .bit file. I am not able to understand how can I decompress the file in FPGA.
Hi , I have gone through this(jpeg_tb) and found that it is reading a .JPG file which is also a binary file and feed each character to data_in. I think I can also read a file in the sameway isn't it?? the out data they are showing in the simulation window. Now for the decoding part how can I go about is. In the code it is doing it the following steps: 1. read a character(c) store it in a prev variable.output the character 'c' 2. read the next character(c) if it is same as 'prev' then output 'prev'. 3. read the next character in (rlecnt) and if rle count != 0 then rlecnt-- and out put the character (c) till rlecnt is 0. Am I interpreted the code correctly? please help...
> I think I can also read a file in the sameway isn't it??
Yes. But ONLY for SIMULATION.
You must be aware that VHDL ist for two worlds: real hardware and
simulation. In simulation you can do anything you want e.g. file access.
But in real hardware you only have binary logic and flipflops. And now:
waht do you have to do to tell those flipflops reading a file? You are
right: that is a big bunch of work...
So once more: do you want to read and write data with a real FPGA. Or do
you just want to SIMULATE the whole thing? Or do ypou want to build the
decoder in a FPGA and simulate a data stream in the simulation? Get
clear about this questions...
If you want to have a program, running on a computer and doing file IO, to read images, then there are better programming languages. If you don't want to put it into a FPGA, why not using the C code? If you want to put it into a FPGA, then forget about file, pictures. First think about the wires and the data format on the wires, where you get the data into your hardware.
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