EmbDev.net

Forum: FPGA, VHDL & Verilog Problem with master-slave latch (VHDL)


Author: Franz Hansel (Guest)
Posted on:

Rate this post
0 useful
not useful
In one of my class I have to program a latch with VHDL without using 
processes, functions etc. So I made the first latch, simulated it, and 
it worked. But for the flip-flop, I have to put two latches together, 
one master and one slave, everything seems to work when I compile but as 
soon as I simulate I get this error.

# KERNEL: Delta count overflow - stopped. Try to increase the iterations 
limit in simulator preferences.
# Fatal error occurred during simulation.

I'm using Active-HDL 8.3 by the way. As far as I know, this happens when 
you have an infinite loop, or something like that, and in my code, I 
think the problem is with the clock I'm using, here's the code:



library IEEE;
use IEEE.std_logic_1164.all;



entity latch is
port(
clk : in std_logic; -- signal reset
D : in std_logic; -- donnee en entree
Q : out std_logic; -- donnee en sortie
notQ : out std_logic -- valeur complement
);
end latch;


architecture latch_arch of latch is
signal DN, SN, RN, IQ, IQN : std_logic;
begin
DN <= not D;
SN <= clk nand D;
IQ <= SN nand IQN;
IQN <=  DN nand IQ;
Q <= IQ;
notQ <= IQN;


end latch_arch;

-----------End for the flip-flop that uses the latch I just made

library IEEE;
use IEEE.std_logic_1164.all;
use LABO44.latch;

entity flipflop is
port(
clk : in std_logic; -- signal d'horloge
D : in std_logic; -- donnee en entree
Q : out std_logic; -- donnee en sortie
notQ : out std_logic -- valeur complement
);
end flipflop;

architecture flipflop_arch of flipflop is
  signal  Din, CN, Qm, QmN, Qs, QsN :std_logic ;
  component latch
  port (clk, D: in std_logic; Q, notQ : out std_logic ); end component;
begin
  Din <= D;
  CN <= not clk;
  U1: latch port map  (CN, Din, Qm, QmN);
  U2: latch port map (clk, Qm, Qs, QsN);
  Q<=Qs;  notQ<=QsN;





end flipflop_arch;



I don't really know what to do with this, It must be a pretty stupid 
error so, any help? Thanks a lot!

Author: Lothar Miller (lkmiller) (Moderator)
Posted on:

Rate this post
0 useful
not useful
> In one of my class I have to program a latch with VHDL without using
> processes, functions etc.
This is my latch:
dout <= din when latchenable='1';

> But for the flip-flop, I have to put two latches together
Why?
This is my flipflop:
dout <= din when rising_edge(clk);

Author: berndl (Guest)
Posted on:

Rate this post
0 useful
not useful
architecture flipflop_arch of flipflop is
  signal  Din, CN, Qm, QmN, Qs, QsN :std_logic ;
  component latch
  port (clk, D: in std_logic; Q, notQ : out std_logic ); end component;
begin
  Din <= D;
  CN <= not clk;
  U1: latch port map  (CN, Din, Qm, QmN);
  U2: latch port map (clk, Qm, Qs, QsN);
  Q<=Qs;  notQ<=QsN;


Do the errors disappear when you add a short delay to the U1 output Qm? 
Like U1: ..... (..., Qm, ...)
Qmdly <= Qm after 1 ps;
U2: ..... (..., Qmdly, ...)

Author: JEMA (Guest)
Posted on:
Attached files:

Rate this post
0 useful
not useful
Your design is not roboust to component delays. You should use two phase 
none overlapping clock to make a roboust design. Then it is more roboust 
than any DFF implementation and will work with higher temperature 
variations.

Reply

Entering an e-mail address is optional. If you want to receive reply notifications by e-mail, please log in.

Rules — please read before posting

  • Post long source code as attachment, not in the text
  • Posting advertisements is forbidden.

Formatting options

  • [c]C code[/c]
  • [avrasm]AVR assembler code[/avrasm]
  • [vhdl]VHDL code[/vhdl]
  • [code]code in other languages, ASCII drawings[/code]
  • [math]formula (LaTeX syntax)[/math]




Bild automatisch verkleinern, falls nötig
Note: the original post is older than 6 months. Please don't ask any new questions in this thread, but start a new one.