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Forum: FPGA, VHDL & Verilog How to connect two modules


Author: deletme (Guest)
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Hi everyone,

As you can see on the attachment file, I'm designing an SPI module that 
is divided in two modules.

But I have a problem when I try to connect data_out with LED (in 
verilog). What I have to use to implement this ?

This is my module declaration :
module SPI(  input clk,
    input SCK,
    input SSEL,
    input MOSI,
    output reg [7:0]LED);

module Read_data (input SCK_SYNC,
    input MOSI,
    input SSEL,
    output reg [7:0] data_out);

module Sync_CLK(input clk,
    input SCK,
    output reg SCK_SYNC);

This my instanciation :
wire SCK_SYNC;
wire[7:0] data_out;

Read_data Read_data1 (.SCK_SYNC(SCK_SYNC), .MOSI(MOSI), .SSEL(SSEL), 
.data_out(LED));
Sync_CLK Sync_CLK1 (.clk(clk),.SCK(SCK), .SCK_SYNC(SCK_SYNC));

But it doesn't work, I have this error :
line 32 Reference to vector reg 'LED' is not a legal net lvalue
line 32 Connection to output port 'data_out' must be a net lvalue
line 32 = Read_data Read_data1 (.SCK_SYNC(SCK_SYNC), .MOSI(MOSI), 
.SSEL(SSEL), .data_out(LED));

I hope that someone can help me

Bye

Author: Ale (Guest)
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Drop the reg from the port declaration.

module SPI(  input clk,
    input SCK,
    input SSEL,
    input MOSI,
    output [7:0]LED);

wire SCK_SYNC;
wire[7:0] led_data;

assign LED = led_data;

Read_data Read_data1 (.SCK_SYNC(SCK_SYNC), .MOSI(MOSI), .SSEL(SSEL),
.data_out(led_data));
Sync_CLK Sync_CLK1 (.clk(clk),.SCK(SCK), .SCK_SYNC(SCK_SYNC));


....

endmodule

***

That should work :)

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