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Forum: FPGA, VHDL & Verilog Generating a signal (a VHDL description) with a well-defined frequency in a FPGA

Generating a signal (a VHDL description) with a well-defined frequency in a FPGA

von issam s. (Company: uqtr) (isamel85)

2011-11-06 05:58

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Hello,
In fact, I'm working on a project that aims to put a communication 
platform to interact with hydrogen sensor wirelessly.
The platform consists of an evaluation board from Xilinx ML505 (on which 
there is a Virtex 5) which will implement the baseband digital 
processing and another board (Software Defined Radio) for the analog 
front end that includes the blocks needed (modulator / demodulator, 
filter, LNA, PA, local oscillator) to communicate on the UHF band (900 
MHz).
The platform requires a 12-bit DAC and an ADC 12-bit to adapt the two 
boards.
So I need help to generate a baseband signal (VHDL description) with a 
defined frequency, otherwise, I have trouble to describe the signal 
generator in VHDL