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Forum: FPGA, VHDL & Verilog Using async signal


Author: Alessio (Guest)
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Hi, i'm new to VHDL, i have this problem:

i've an async signal, called REQUEST, and into my process, if the 
counter arrives to 5 and if the REQUEST signal went 1 in the previous 
period of clock, i must do something. my problem is that REQUEST is 
asynchronous, and its period should be less long than clock's period, so 
i can't check it every positive edge of clock with the usual clock'event 
and clock='1'….

how can i solve this problem? thanks!

Author: Lothar Miller (lkmiller) (Moderator)
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> and if the REQUEST signal went 1 in the previous
> period of clock, i must do something.
Lets say these are your signals:  (X=signal change)
CLK   .-------.         ,-------.         ,-------.         ,-------.
     ´         `-------´         `-------´         `-------´
CNT    X     3           X     4           X      5          X
REQUEST   when does it get active?   ^here     ^or here

> and its period should be less long than clock's period, so i can't
> check it every positive edge of clock with the usual clock'event
> and clock='1'….
You can store a pulse in a signal shorter than your clock cycle in a way 
like this:
http://www.lothar-miller.de/s9y/archives/19-Kurzer...
But even a trick like this doesn't help you with your problem of clock 
donaim crossing. As you describe it, I see no chance to react reliable 
in less than one clock cycle...

Author: Alessio (Guest)
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i don't know when request go 1, it's the problem…

i think also that the link contains the solution for my problem, thanks!

Author: Sim (Guest)
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Hallo,

check the signal with a much faster clock and store it with an flip 
flop. Is that no option?

Or use the request signal in the following way "request'event" and set a 
flag.

Sim

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