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Forum: FPGA, VHDL & Verilog help needed for a non restoring division


Author: Aswin Kavali (Company: nit warangal) (aswinkavali)
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity nam is
port (a : in std_logic_vector(7 downto 0);
    b : in std_logic_vector(3 downto 0);
    c : out std_logic_vector(3 downto 0));
end nam;


architecture ban of nam is
begin
process(a,b)
variable p,h :std_logic_vector(8 downto 0);
variable m :std_logic_vector(4 downto 0);
variable k:std_logic;


begin
m(4):='0';
m(3 downto 0):=b;
p(8):='0';
p(7 downto 0):=a;
p(8 downto 4):=p(8 downto 4)-m;
k:=p(8);
p(8 downto 1):=p(7 downto 0);
h:=p;
for i in 0 to 4 loop
if(k='0') then
h(0):='1';
h(8 downto 4):=h(8 downto 4)-m;
else
h(1):='0';
h(8 downto 4):=h(8 downto 4)+m;
end if;
k:=h(8);
h(8 downto 1):=h(7 downto 0);

if (i=4) then
c<=h(3 downto 0);
end if;
end loop;

end process;

end ban;

c=quotient
c=a/b



here i have written one program for non restoring division....but am 
getting the quotient as three....

Author: Lothar Miller (lkmiller) (Moderator)
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> here i have written one program for non restoring division...
You run a division of 8 bits by 4 bits and you return 4 bits as the 
result.
         a : IN  std_logic_vector(7 downto 0);
         b : IN  std_logic_vector(3 downto 0);
         c : OUT  std_logic_vector(3 downto 0)
So one fairly simple question:
What would you expect as result when you calculate 16/1 or 32/2 or 33/2?
How will these results fit in 4 bit?

Author: Aswin Kavali (Company: nit warangal) (aswinkavali)
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that one is a limitation....but i have tried 32 by 4 and 32 by 8 the 
resuts were 3 in both cases.......what will be the problem...anybody 
having another program for this non restoring division please send 
me.....

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