EmbDev.net

Forum: FPGA, VHDL & Verilog VHDL Project with Verilog IP


Author: John Douglas (Guest)
Posted on:

Rate this post
0 useful
not useful
Hi there,

I have a project in VHDL and I want to buy some IP from Synopsys but the 
IP is written in Verilog.

Would I be able to use it in the project and synthesize it?

Thank you.

Regards,
John

Author: user (Guest)
Posted on:

Rate this post
0 useful
not useful
It is possible, for FPGAs Xilinx and Altera allow a mixed synthesis 
(VHDL / Verilog)

Author: John (Guest)
Posted on:

Rate this post
0 useful
not useful
Thanks a lot.

Reply

Entering an e-mail address is optional. If you want to receive reply notifications by e-mail, please log in.

Rules — please read before posting

  • Post long source code as attachment, not in the text
  • Posting advertisements is forbidden.

Formatting options

  • [c]C code[/c]
  • [avrasm]AVR assembler code[/avrasm]
  • [vhdl]VHDL code[/vhdl]
  • [code]code in other languages, ASCII drawings[/code]
  • [math]formula (LaTeX syntax)[/math]




Bild automatisch verkleinern, falls nötig
Note: the original post is older than 6 months. Please don't ask any new questions in this thread, but start a new one.