Forum: FPGA, VHDL & Verilog Beginner's problem with very simple Verilog buffer

Author: jhin (Guest)
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Hey everyone,

I've got a hopefully easy to solve question.
The following Code is given:

module filter
    input                 clk,
    input                 en,
    input [31:0]          rawdata,
    output [31:0]         filtered_data
  reg [31:0]              filtered_data_q;

  assign filtered_data    = filtered_data_q;

  // filter + register
  always @(posedge clk)
    if (en)
      // Simple recursive filtering
      filtered_data_q <= filtered_data_q * 3 / 4 + rawdata / 4;
      filtered_data_q <= filtered_data_q;

This code synthesizes and simulates perfectly, just as expected.
But once I add a simple(st) buffer, nothing works:

  wire    temp;
  assign  temp = rawdata;
Additionally, I used 'temp' instead of 'rawdata' for the filter.

The result is that my complete filtered_q register is removed during 
optimization step for the following reason: "Stuck at GND due to stuck 
port data_in"

I also tried
  reg temp;
  always @ (rawdata)
    temp = rawdata;
but that did not change anything.

Any Explanations? Why does this happen?

Author: Uwe Bonnes (Guest)
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Did youb really write
and not
Do temp at max resolves to `'b1 and
1'b1 >>4
is alway 0!

Author: jhin (Guest)
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Haha, you're right!
I expected it to be a stupid mistake, not knowing it could be THAT 
stupid ... :-)
Anyway, thanks a lot for pointing it out!


Author: beginner (Guest)
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Hallo Uwe,

can you explain that is the different between

wire  and wire[31:0]   ?

thank you

Author: not Uwe (Guest)
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wire means only 1 bit
wire[31:0] means 32 bits

because verilog doesn't talk and disallow as much as vhdl, it is 
accepted to fed a 32bit vector into a 1 bit(keeping only 1 bit!).

So all other 31 bits are lost and you will never know it.
(maybe there is a warning from synthesis tool, don't know)


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