splee splee wrote:
> Two questions here:
> 1. So the two codes below essentially are identical to each other
> (synthesized circuit)?
They are exactly the same.
Additionally this results in exactly the same hardware (just wiring...)
1 | architecture Behav1 of simpleBuffer is
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2 | signal b : STD_LOGIC;
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3 | begin
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4 | process (a)
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5 | begin
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6 | b <= a;
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7 | end process;
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8 |
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9 | process (b)
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10 | begin
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11 | c <= b;
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12 | end process;
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13 | end Behavioral;
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And also this:
1 | process (a,b)
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2 | begin
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3 | b <= a;
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4 | c <= b;
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5 | end process;
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is the same like this:
1 | process (a,b)
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2 | begin
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3 | c <= b;
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4 | b <= a;
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5 | end process;
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> 2. In a process statement, a signal only gets its assigned value after
> the process suspends, eg. in Behav1, b only gets the value of a after
> the process suspends.
> Why would a synthesis tool make it such complicated?
Because thats the behaviour defined in the language description of VHDL.
> I mean, why can't a signal get the value immediately,
> just like variable and like in C program?
If you use signals and a clock you can be sure: theres no need to
observe the order of the instructions, because throughout the whole
process the signal doesn't change its value. So this:
1 | signal a,b,clk : ...
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2 | :
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3 | process (clk) begin
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4 | if rising_edge(clk) then
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5 | b <= b+1;
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6 | if (b=4) then
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7 | a <= a+1;
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8 | end if;
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9 | end if;
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10 | end process;
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is exactly the same like this:
1 | signal a,b,clk : ...
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2 | :
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3 | process (clk) begin
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4 | if rising_edge(clk) then
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5 | if (b=4) then
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6 | a <= a+1;
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7 | end if;
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8 | b <= b+1;
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9 | end if;
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10 | end process;
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With variables you must be aware, where to add statements.
> What's the point of making things difficult?
Its not difficult, its just different... ;-)