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Forum: FPGA, VHDL & Verilog simple code, pls help


Author: splee splee (Company: ss) (splee)
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Hi,

I am a beginner of VHDL.

I wrote a simple code below. The compiler warns me that 'b' should be in 
the sensitivity list. Why is this so?

What will be RTL schematic circuit be in this case?

entity simpleBuffer is
    Port ( a : in  STD_LOGIC;
           c : out  STD_LOGIC);
end simpleBuffer;

architecture Behavioral of simpleBuffer is
signal b    : STD_LOGIC;
begin
    process (a)
    begin
            b <= a;
            c <= b;
    end process;
end Behavioral;

Author: Lothar Miller (lkmiller) (Moderator)
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splee splee wrote:
> The compiler warns me that 'b' should be in
> the sensitivity list. Why is this so?
Why do you do 'a' in the sensitivity list?

> The compiler warns me that 'b' should be in
> the sensitivity list. Why is this so?
1. Because otherwise the simulation is wrong. In this code the output 
takes over the last value of b on a change of the input a, but
2. that doesn't represent the actual hardware implemented by the 
synthesizer. Actually theres only a dirct connection from input a to 
output c


> What will be RTL schematic circuit be in this case?
         
     a        a->b->c         c
    <Input>---<Alias>---<Output>

BTW: is this homework? Both of the questions are easily answered by 
playing with the simulator and the synthesizer...

Author: splee splee (Company: ss) (splee)
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Hi Miller,
I don't understand why it is a direct connection from input a to output 
c. Please see my argument, and see if it is wrong:

- when a changes, the entire process statement is evaluated. b is 
schedule to get the new value of a, c is scheduled to get the current 
value of b
- when process suspends, b is equal to a, both have the new value. And c 
is equal to previous value of b.
- c will not be equal to b (or a) because the process statement is only 
evaluated once (since b is not in the sensitivity list)
- so a to b is a direct connection, whereas from b to c is something 
else.

..? Not sure if my argument is valid. Please comment.

Author: Stefan Helmert (Company: dm2sh) (stefan_helmert)
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The compiler (synthesis toll) does ignore the sensitivity list!
The process is "running" all the time.

Author: Lothar Miller (lkmiller) (Moderator)
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splee splee wrote:
> ..? Not sure if my argument is valid. Please comment.
Try it yourself. Have a look at the RTL schematics.

And as already stated:
The sensitivity list is only used by the simulation.
The synthesizer "adds" all of the missing singals to the list on its 
own. The synthesizer just generates an info, that some signals are 
missing.

Author: splee splee (Company: ss) (splee)
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Two questions here:
1. So the two codes below essentially are identical to each other 
(synthesized circuit)?
architecture Behav1 of simpleBuffer is
signal b    : STD_LOGIC;
begin
    process (a,b)
    begin
            b <= a;
            c <= b;
    end process;
end Behavioral;
architecture Behav2 of simpleBuffer is
signal b    : STD_LOGIC;
begin
            b <= a;
            c <= b;
end Behavioral;

2. In a process statement, a signal only gets its assigned value after 
the process suspends, eg. in Behav1, b only gets the value of a after 
the process suspends.
Why would a synthesis tool make it such complicated? I mean, why can't a 
signal get the value immediately, just like variable and like in C 
program?
What's the point of making things difficult?

Author: berndl (Guest)
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> Why would a synthesis tool make it such complicated? I mean, why can't a
> signal get the value immediately, just like variable and like in C
> program?
> What's the point of making things difficult?

Probably because SW is sequential and HW is parallel?

Author: Lothar Miller (lkmiller) (Moderator)
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splee splee wrote:
> Two questions here:
> 1. So the two codes below essentially are identical to each other
> (synthesized circuit)?
They are exactly the same.
Additionally this results in exactly the same hardware (just wiring...)
architecture Behav1 of simpleBuffer is
signal b    : STD_LOGIC;
begin
    process (a)
    begin
            b <= a;
    end process;   
 
    process (b)
    begin
            c <= b;
    end process;
end Behavioral;

And also this:
    process (a,b)
    begin
            b <= a;
            c <= b;
    end process;
is the same like this:
    process (a,b)
    begin
            c <= b;  
            b <= a;
    end process;

> 2. In a process statement, a signal only gets its assigned value after
> the process suspends, eg. in Behav1, b only gets the value of a after
> the process suspends.
> Why would a synthesis tool make it such complicated?
Because thats the behaviour defined in the language description of VHDL.

> I mean, why can't a signal get the value immediately,
> just like variable and like in C program?
If you use signals and a clock you can be sure: theres no need to 
observe the order of the instructions, because throughout the whole 
process the signal doesn't change its value. So this:
 signal a,b,clk : ...
  :
  process (clk) begin
    if rising_edge(clk) then
      b <= b+1;
      if (b=4) then
         a <= a+1;
      end if;
    end if;
  end process;
is exactly the same like this:
 signal a,b,clk : ...
  :
  process (clk) begin
    if rising_edge(clk) then
      if (b=4) then
         a <= a+1;
      end if;
      b <= b+1;
    end if;
  end process;
With variables you must be aware, where to add statements.

> What's the point of making things difficult?
Its not difficult, its just different... ;-)

Author: splee splee (Company: ss) (splee)
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Dear Miller,
But I thought within a process statement, all the expressions must be 
read sequentially, so is it just contradicting to what you mentioned 
that the following are the same? Otherwise I could just read them upside 
down?
  process (clk) begin
    if rising_edge(clk) then
      if (b=4) then
         a <= a+1;
      end if;
      b <= b+1;
    end if;
  end process;
  process (clk) begin
    if rising_edge(clk) then
      b <= b+1;
      if (b=4) then
         a <= a+1;
      end if;
    end if;
  end process;

Author: Lothar Miller (lkmiller) (Moderator)
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> But I thought within a process statement, all the expressions must be
> read sequentially
Yes, thats right, but every signal keeps its old value throughout 
the whole process. The new values calculated in the process are 
assigned to the signal after finishing the process. So also this is the 
same as the descriptions above:
  process (clk) begin
    if rising_edge(clk) then
      b <= b+1;
      if (b=4) then
         a <= a+1;
         b <= b+1;
      end if;
      b <= b+1;
    end if;
  end process;

All of the processes above read essentially like this:
  process (clk) 
  variable temp_b;
  begin
    if rising_edge(clk) then
      new_b := b+1;          -- calc a new value based on the old value
      if (b=4) then          -- takt the old vale for the compare
         a <= a+1;
         new_b := b+1;       -- calc a new value based on the old value
      end if;
      new_b := b+1;          -- calc a new value based on the old value
    end if;
    b <= new_b;
  end process;
A new b is calcutlated, but for all of the calculations the old b is 
taken as a basis.

> Otherwise I could just read them upside down?
If only signals are involved: Yes.

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