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Forum: FPGA, VHDL & Verilog help with multiplier


Author: sreeram sam (sresam89)
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the program is for a  simple multiplier using addition of the partial 
products. i find problem only with final addition part pls help me out
architecture Behavioral of new_twin1 is
type arr is array (3 downto 0) of std_logic_vector(3 downto 0);
type arr2 is array(4 downto 0) of std_logic_vector(7 downto 0);
signal and_1:arr:=("0000","0000","0000","0000");
signal t6:arr2:=("00000000","00000000","00000000","00000000","00000000");
signal temp:std_logic_vector(3 downto 0);
signal sum:std_logic_vector(7 downto 0):="00000000";
begin
process(clk)
variable z,t,k:integer;
variable t2:std_logic_vector(3 downto 0):="0000";
variable t7:std_logic_vector(7 downto 0);--:="00000000";
begin
for i in 0 to 3 loop
t6(i)(7 downto 0)<=("00000000");
end loop;
for i in 0 to 3 loop
 for j in 0 to 3 loop
  and_1(i)(j)<=(x(i) and y(j));
 end loop;
end loop;
t6(3)<=  "0000" & and_1(0);
k:=0; 
for i in 2 downto 0 loop
 t6(i)<=t2( i downto 0) & and_1(k+1) & t2(k downto 0);
 k:=k+1;
end loop;
for i in 0 to 3 loop
 t6(4)<=t6(4)+t6(i);
end loop
----just tried this alternative which too dint work---
--  t6(4)<=t6(0);
--  t6(4)<=t6(4)+t6(1);
--  t6(4)<=t6(4)+t6(2);
--  t6(4)<=t6(4)+t6(3);
end process;
end Behavioral;

the final for loop for addition is giving me a gig-up.when i try to 
access one variable inside the array am able to retrieve it but while 
adding to the same, the total value tends to undefined(XXXXXXXX).
please suggest any modification
thanks in advance

Author: Duke Scarring (Guest)
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Can you provide a working testbench?

Duke

Author: sreeram sam (sresam89)
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Duke Scarring wrote:
> Can you provide a working testbench?
>
> Duke

i did not get you

moreover i solved it by changing the data types for t6 to variable 
rather using signal

Author: Lothar Miller (lkmiller) (Moderator)
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> process(clk)
Your process isn't sensitive to the clock.
So your sensitivity list is WRONG and therfore the whole simulation is 
completely WRONG.


> moreover i solved it by changing the data types for t6 to variable
> rather using signal
Sounds like "I'm digging for gold, but don't know where"....

Author: sreeram sam (sresam89)
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Lothar Miller wrote:
>> process(clk)
> Your process isn't sensitive to the clock.
> So your sensitivity list is WRONG and therfore the whole simulation is
> completely WRONG.
>
>
>> moreover i solved it by changing the data types for t6 to variable
>> rather using signal
> Sounds like "I'm digging for gold, but don't know where"....

SORRRY MORE OR LESS THE SAME :)

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