Forum: FPGA, VHDL & Verilog how to include verilogCSP macros in standard verilog

Author: vidhya annamalai (Company: student) (vidhya)
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i'm in need to design a asynchronous router using verilogCSP.... To use 
this language i need to include some macros in standard verilog if i 
include this macros file using `include i'm getting error in tne macros 
file itself... here i'm attaching the macros file that is to be 
included... pls give me some suggestion how the macros can be included


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