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Forum: FPGA, VHDL & Verilog [VHDL] Beginner: "Syntax error near use "


Author: John Edwards (edwards)
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Hello All,

As a beginner, I am trying to simulate an XOR gate using AND gates and 
OR gate that I created in vhdl modules and_gate and or_gate 
respectively.

I have a syntax error ("Syntax error near use") on line 62  (marked 
"--Error--") of the testbench file which I am unable to resolve.

Can anyone spot the mistake?

TESTBENCH FILE
---------------

Here is the code:
--X--
entity tb_xor_gate is
end tb_xor_gate;

architecture Behavioral of tb_xor_gate is
  component xor_gate
    port (output: out bit; 
        input_a, input_b: in bit);
  end component;
  
  signal signal_a, signal_b, output: bit;
begin
  XG1: xor_gate port map (input_a => signal_a, input_b => signal_b, 
                  output => output);
  
  DUT: process
    begin
    signal_a <= '0'; signal_b <= '0';
    wait for 10 ns;
    signal_a <= '0'; signal_b <= '1';
    wait for 10 ns;
    signal_a <= '1'; signal_b <= '0';
    wait for 10 ns;
    signal_a <= '1'; signal_b <= '1';
    wait for 10 ns;
  end process DUT;
end Behavioral;

configuration cfg_tb_xor_gate of tb_xor_gate is
  for Behavioral
    for DUT:
      use entity work.xor_gate(Behavioral2); --Error--
    end for;
  end for;
end cfg_tb_xor_gate;
--X--

Here is my .vhd File for xor_gate that compiles successfully. The AND 
gates and OR gates also compile without any issues.
--X--
entity xor_gate is
  port(output: out bit; 
      input_a, input_b: in bit);
end xor_gate;

architecture Behavioral2 of xor_gate is
  component or_gate 
    port (output: out bit; 
        input_a, input_b: in bit);
  end component;
  
  component and_gate 
    port (output: out bit; 
        input_a, input_b: in bit);
  end component;
  
  signal a_not_b, b_not_a: bit;
  signal not_inp_a, not_inp_b: bit;
begin
  not_inp_a <= not input_a;
  not_inp_b <= not input_b;
  
  G1: and_gate port map(a_not_b, input_a, not_inp_b);
  G2: and_gate port map(b_not_a, input_b, not_inp_a);
  G3: or_gate port map(output, a_not_b, b_not_a);
end Behavioral2;

configuration cfg_xor_gate of xor_gate is
  for Behavioral2
    for G1: and_gate
      use entity work.and_gate(Behavioral);
    end for;
    
    for G2: and_gate 
      use entity work.and_gate(Behavioral);
    end for;
    
    for G3: or_gate
      use entity work.or_gate(Behavioral);
    end for;
  end for;
end configuration;
--X--

Thanks

Author: John Edwards (edwards)
Posted on:

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Hello All,

I spotted the mistake.

The "configuration" block in test bench is completely wrong. I am trying 
to assign a configuration of an xor gate for an xor gate used in block 
DUT.

But DUT is a process in testbench with no xor gate. Hence, I retyped the 
configuration block in the testbench file as:

------------------------------------------------
configuration cfg_tb_xor_gate of tb_xor_gate is
  for Behavioral
    for XG1:xor_gate
      use entity work.xor_gate(Behavioral2);
    end for;
  end for;
end cfg_tb_xor_gate;
------------------------------------------------

The code now compiles.

Regards,

Edwards

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