Hello All, As a beginner, I am trying to simulate an XOR gate using AND gates and OR gate that I created in vhdl modules and_gate and or_gate respectively. I have a syntax error ("Syntax error near use") on line 62 (marked "--Error--") of the testbench file which I am unable to resolve. Can anyone spot the mistake? TESTBENCH FILE --------------- Here is the code: --X--
1 | entity tb_xor_gate is |
2 | end tb_xor_gate; |
3 | |
4 | architecture Behavioral of tb_xor_gate is |
5 | component xor_gate |
6 | port (output: out bit; |
7 | input_a, input_b: in bit); |
8 | end component; |
9 | |
10 | signal signal_a, signal_b, output: bit; |
11 | begin
|
12 | XG1: xor_gate port map (input_a => signal_a, input_b => signal_b, |
13 | output => output); |
14 | |
15 | DUT: process |
16 | begin
|
17 | signal_a <= '0'; signal_b <= '0'; |
18 | wait for 10 ns; |
19 | signal_a <= '0'; signal_b <= '1'; |
20 | wait for 10 ns; |
21 | signal_a <= '1'; signal_b <= '0'; |
22 | wait for 10 ns; |
23 | signal_a <= '1'; signal_b <= '1'; |
24 | wait for 10 ns; |
25 | end process DUT; |
26 | end Behavioral; |
27 | |
28 | configuration cfg_tb_xor_gate of tb_xor_gate is |
29 | for Behavioral |
30 | for DUT: |
31 | use entity work.xor_gate(Behavioral2); --Error-- |
32 | end for; |
33 | end for; |
34 | end cfg_tb_xor_gate; |
--X-- Here is my .vhd File for xor_gate that compiles successfully. The AND gates and OR gates also compile without any issues. --X--
1 | entity xor_gate is |
2 | port(output: out bit; |
3 | input_a, input_b: in bit); |
4 | end xor_gate; |
5 | |
6 | architecture Behavioral2 of xor_gate is |
7 | component or_gate |
8 | port (output: out bit; |
9 | input_a, input_b: in bit); |
10 | end component; |
11 | |
12 | component and_gate |
13 | port (output: out bit; |
14 | input_a, input_b: in bit); |
15 | end component; |
16 | |
17 | signal a_not_b, b_not_a: bit; |
18 | signal not_inp_a, not_inp_b: bit; |
19 | begin
|
20 | not_inp_a <= not input_a; |
21 | not_inp_b <= not input_b; |
22 | |
23 | G1: and_gate port map(a_not_b, input_a, not_inp_b); |
24 | G2: and_gate port map(b_not_a, input_b, not_inp_a); |
25 | G3: or_gate port map(output, a_not_b, b_not_a); |
26 | end Behavioral2; |
27 | |
28 | configuration cfg_xor_gate of xor_gate is |
29 | for Behavioral2 |
30 | for G1: and_gate |
31 | use entity work.and_gate(Behavioral); |
32 | end for; |
33 | |
34 | for G2: and_gate |
35 | use entity work.and_gate(Behavioral); |
36 | end for; |
37 | |
38 | for G3: or_gate |
39 | use entity work.or_gate(Behavioral); |
40 | end for; |
41 | end for; |
42 | end configuration; |
--X-- Thanks