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Forum: FPGA, VHDL & Verilog matrix Diagonal addition


Author: sreeram sam (sresam89)
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can somebody help me with a loop for diagonal addtion of a matrix datas.

i need to add the datas of an array but in diagonal fashion say i have a 
3X3 array.


a[3][3]=

0   1    2   3
4   5    6   7
8   9   10  11
12  13  14  15

the answer should be like

0=t0;
4+1=t2
8+5+2=t3;
12+9+6+3=t4;
13+10+7=t5;
14+11=t6;
15=t7;

ie in looply manners

a[0][0]=t[0];

a[1][0]+a[0][1]=t[1];

a[2][0]+a[1][1]+a[0][2]=t2;

a[3][0]+a[2][1]+a[1][2]+a[0][3]=t3;

a[3][1]+a[2][2]+a[1][3]=t4;

a[3][2]+a[2][3]=t5;

a[3][3]=t6;

sorry to make you work

and thanks a lot in advance

Author: abc (Guest)
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for i in 0 to array_size-1 loop

   sum[i] := 0

   for x in 0 to array_size-1 loop

      y := i - x

      if (y>=0) then
         sum[i] := sum[i] + a[x][y];
      end if;

   end loop;
end loop;


array_size is 4 in this case.

untested, but should work.
It sums for all "rising" diagonals but drops fields that are not in the 
array.

this is the only one part of the calcs (t0-t3).

You need to copy this and use
y := i + x
as well as
if (y<=array_size-1)

for t3-t6 and ignore the sum that appears double(t3) for one of both.

Author: sreeram sam (sresam89)
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abc wrote:
> for i in 0 to array_size-1 loop
>
>    sum[i] := 0
>
>    for x in 0 to array_size-1 loop
>
>       y := i - x
>
>       if (y>=0) then
>          sum[i] := sum[i] + a[x][y];
>       end if;
>
>    end loop;
> end loop;
>
>
> array_size is 4 in this case.
>
> untested, but should work.
> It sums for all "rising" diagonals but drops fields that are not in the
> array.
>
> this is the only one part of the calcs (t0-t3).
>
> You need to copy this and use
> y := i + x
> as well as
> if (y<=array_size-1)
>
> for t3-t6 and ignore the sum that appears double(t3) for one of both.


thanks it helped a lot.. but one more doubt prevails..
when i use the statement
sum(i) <= sum(i) + and1(x,y);
 the compiler gives me an error
"Line 63. + can not have such operands in this context".

sum is been declared as a signal,and1 as an variable of type 
std_logic_vector

pls help

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